T208xQDS.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * T2080/T2081 QDS board configuration file
  8. */
  9. #ifndef __T208xQDS_H
  10. #define __T208xQDS_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #if defined(CONFIG_ARCH_T2080)
  14. #define CONFIG_FSL_SATA_V2
  15. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  16. #define CONFIG_SRIO1 /* SRIO port 1 */
  17. #define CONFIG_SRIO2 /* SRIO port 2 */
  18. #endif
  19. /* High Level Configuration Options */
  20. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  21. #define CONFIG_ENABLE_36BIT_PHYS
  22. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  23. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  24. #ifdef CONFIG_RAMBOOT_PBL
  25. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_PAD_TO 0x40000
  28. #define CONFIG_SPL_MAX_SIZE 0x28000
  29. #define RESET_VECTOR_OFFSET 0x27FFC
  30. #define BOOT_PAGE_OFFSET 0x27000
  31. #ifdef CONFIG_SPL_BUILD
  32. #define CONFIG_SPL_SKIP_RELOCATE
  33. #define CONFIG_SPL_COMMON_INIT_DDR
  34. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  35. #endif
  36. #ifdef CONFIG_MTD_RAW_NAND
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  38. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  39. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  40. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  41. #if defined(CONFIG_ARCH_T2080)
  42. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  43. #endif
  44. #endif
  45. #ifdef CONFIG_SPIFLASH
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  47. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  49. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  51. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  52. #ifndef CONFIG_SPL_BUILD
  53. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54. #endif
  55. #if defined(CONFIG_ARCH_T2080)
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  57. #endif
  58. #endif
  59. #ifdef CONFIG_SDCARD
  60. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  61. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  62. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  63. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  64. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  65. #ifndef CONFIG_SPL_BUILD
  66. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67. #endif
  68. #if defined(CONFIG_ARCH_T2080)
  69. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  70. #endif
  71. #endif
  72. #endif /* CONFIG_RAMBOOT_PBL */
  73. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  74. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  75. /* Set 1M boot space */
  76. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  77. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  78. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  79. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  80. #endif
  81. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  82. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  83. #endif
  84. /*
  85. * These can be toggled for performance analysis, otherwise use default.
  86. */
  87. #define CONFIG_SYS_CACHE_STASHING
  88. #define CONFIG_BTB /* toggle branch predition */
  89. #define CONFIG_DDR_ECC
  90. #ifdef CONFIG_DDR_ECC
  91. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  92. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  93. #endif
  94. #ifndef __ASSEMBLY__
  95. unsigned long get_board_sys_clk(void);
  96. unsigned long get_board_ddr_clk(void);
  97. #endif
  98. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  99. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  100. /*
  101. * Config the L3 Cache as L3 SRAM
  102. */
  103. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  104. #define CONFIG_SYS_L3_SIZE (512 << 10)
  105. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  106. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  107. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  108. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  109. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  110. #define CONFIG_SYS_DCSRBAR 0xf0000000
  111. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  112. /* EEPROM */
  113. #define CONFIG_ID_EEPROM
  114. #define CONFIG_SYS_I2C_EEPROM_NXID
  115. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  116. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  117. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  118. /*
  119. * DDR Setup
  120. */
  121. #define CONFIG_VERY_BIG_RAM
  122. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  123. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  124. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  125. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  126. #define CONFIG_DDR_SPD
  127. #define CONFIG_SYS_SPD_BUS_NUM 0
  128. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  129. #define SPD_EEPROM_ADDRESS1 0x51
  130. #define SPD_EEPROM_ADDRESS2 0x52
  131. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  132. #define CTRL_INTLV_PREFERED cacheline
  133. /*
  134. * IFC Definitions
  135. */
  136. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  137. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  138. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  139. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  140. + 0x8000000) | \
  141. CSPR_PORT_SIZE_16 | \
  142. CSPR_MSEL_NOR | \
  143. CSPR_V)
  144. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  145. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  146. CSPR_PORT_SIZE_16 | \
  147. CSPR_MSEL_NOR | \
  148. CSPR_V)
  149. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  150. /* NOR Flash Timing Params */
  151. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  152. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  153. FTIM0_NOR_TEADC(0x5) | \
  154. FTIM0_NOR_TEAHC(0x5))
  155. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  156. FTIM1_NOR_TRAD_NOR(0x1A) |\
  157. FTIM1_NOR_TSEQRAD_NOR(0x13))
  158. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  159. FTIM2_NOR_TCH(0x4) | \
  160. FTIM2_NOR_TWPH(0x0E) | \
  161. FTIM2_NOR_TWP(0x1c))
  162. #define CONFIG_SYS_NOR_FTIM3 0x0
  163. #define CONFIG_SYS_FLASH_QUIET_TEST
  164. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  165. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  166. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  167. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  168. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  169. #define CONFIG_SYS_FLASH_EMPTY_INFO
  170. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  171. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  172. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  173. #define QIXIS_BASE 0xffdf0000
  174. #define QIXIS_LBMAP_SWITCH 6
  175. #define QIXIS_LBMAP_MASK 0x0f
  176. #define QIXIS_LBMAP_SHIFT 0
  177. #define QIXIS_LBMAP_DFLTBANK 0x00
  178. #define QIXIS_LBMAP_ALTBANK 0x04
  179. #define QIXIS_LBMAP_NAND 0x09
  180. #define QIXIS_LBMAP_SD 0x00
  181. #define QIXIS_RCW_SRC_NAND 0x104
  182. #define QIXIS_RCW_SRC_SD 0x040
  183. #define QIXIS_RST_CTL_RESET 0x83
  184. #define QIXIS_RST_FORCE_MEM 0x1
  185. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  186. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  187. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  188. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  189. #define CONFIG_SYS_CSPR3_EXT (0xf)
  190. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  191. | CSPR_PORT_SIZE_8 \
  192. | CSPR_MSEL_GPCM \
  193. | CSPR_V)
  194. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  195. #define CONFIG_SYS_CSOR3 0x0
  196. /* QIXIS Timing parameters for IFC CS3 */
  197. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  198. FTIM0_GPCM_TEADC(0x0e) | \
  199. FTIM0_GPCM_TEAHC(0x0e))
  200. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  201. FTIM1_GPCM_TRAD(0x3f))
  202. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  203. FTIM2_GPCM_TCH(0x8) | \
  204. FTIM2_GPCM_TWP(0x1f))
  205. #define CONFIG_SYS_CS3_FTIM3 0x0
  206. /* NAND Flash on IFC */
  207. #define CONFIG_NAND_FSL_IFC
  208. #define CONFIG_SYS_NAND_BASE 0xff800000
  209. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  210. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  211. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  212. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  213. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  214. | CSPR_V)
  215. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  216. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  217. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  218. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  219. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  220. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  221. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  222. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  223. #define CONFIG_SYS_NAND_ONFI_DETECTION
  224. /* ONFI NAND Flash mode0 Timing Params */
  225. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  226. FTIM0_NAND_TWP(0x18) | \
  227. FTIM0_NAND_TWCHT(0x07) | \
  228. FTIM0_NAND_TWH(0x0a))
  229. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  230. FTIM1_NAND_TWBE(0x39) | \
  231. FTIM1_NAND_TRR(0x0e) | \
  232. FTIM1_NAND_TRP(0x18))
  233. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  234. FTIM2_NAND_TREH(0x0a) | \
  235. FTIM2_NAND_TWHRE(0x1e))
  236. #define CONFIG_SYS_NAND_FTIM3 0x0
  237. #define CONFIG_SYS_NAND_DDR_LAW 11
  238. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  239. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  240. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  241. #if defined(CONFIG_MTD_RAW_NAND)
  242. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  243. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  244. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  245. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  246. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  247. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  248. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  249. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  250. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  251. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  252. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  253. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  254. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  255. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  256. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  257. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  258. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  259. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  260. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  261. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  262. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  263. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  264. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  265. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  266. #else
  267. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  268. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  269. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  270. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  271. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  272. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  273. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  274. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  275. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  276. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  277. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  278. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  279. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  280. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  281. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  282. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  283. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  284. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  285. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  286. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  287. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  288. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  289. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  290. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  291. #endif
  292. #if defined(CONFIG_RAMBOOT_PBL)
  293. #define CONFIG_SYS_RAMBOOT
  294. #endif
  295. #ifdef CONFIG_SPL_BUILD
  296. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  297. #else
  298. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  299. #endif
  300. #define CONFIG_HWCONFIG
  301. /* define to use L1 as initial stack */
  302. #define CONFIG_L1_INIT_RAM
  303. #define CONFIG_SYS_INIT_RAM_LOCK
  304. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  305. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  306. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  307. /* The assembler doesn't like typecast */
  308. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  309. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  310. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  311. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  312. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  313. GENERATED_GBL_DATA_SIZE)
  314. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  315. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  316. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  317. /*
  318. * Serial Port
  319. */
  320. #define CONFIG_SYS_NS16550_SERIAL
  321. #define CONFIG_SYS_NS16550_REG_SIZE 1
  322. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  323. #define CONFIG_SYS_BAUDRATE_TABLE \
  324. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  325. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  326. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  327. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  328. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  329. /*
  330. * I2C
  331. */
  332. #if !CONFIG_IS_ENABLED(DM_I2C)
  333. #define CONFIG_SYS_I2C_LEGACY
  334. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  335. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  336. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  337. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  338. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  339. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  340. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  341. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  342. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  343. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  344. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  345. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  346. #endif
  347. #define CONFIG_SYS_I2C_FSL
  348. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  349. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  350. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  351. #define I2C_MUX_CH_DEFAULT 0x8
  352. #define I2C_MUX_CH_VOL_MONITOR 0xa
  353. /* Voltage monitor on channel 2*/
  354. #define I2C_VOL_MONITOR_ADDR 0x40
  355. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  356. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  357. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  358. #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
  359. #ifndef CONFIG_SPL_BUILD
  360. #define CONFIG_VID
  361. #endif
  362. #define CONFIG_VOL_MONITOR_IR36021_SET
  363. #define CONFIG_VOL_MONITOR_IR36021_READ
  364. /* The lowest and highest voltage allowed for T208xQDS */
  365. #define VDD_MV_MIN 819
  366. #define VDD_MV_MAX 1212
  367. /*
  368. * RapidIO
  369. */
  370. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  371. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  372. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  373. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  374. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  375. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  376. /*
  377. * for slave u-boot IMAGE instored in master memory space,
  378. * PHYS must be aligned based on the SIZE
  379. */
  380. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  381. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  382. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  383. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  384. /*
  385. * for slave UCODE and ENV instored in master memory space,
  386. * PHYS must be aligned based on the SIZE
  387. */
  388. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  389. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  390. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  391. /* slave core release by master*/
  392. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  393. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  394. /*
  395. * SRIO_PCIE_BOOT - SLAVE
  396. */
  397. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  398. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  399. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  400. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  401. #endif
  402. /*
  403. * eSPI - Enhanced SPI
  404. */
  405. /*
  406. * General PCI
  407. * Memory space is mapped 1-1, but I/O space must start from 0.
  408. */
  409. #define CONFIG_PCIE1 /* PCIE controller 1 */
  410. #define CONFIG_PCIE2 /* PCIE controller 2 */
  411. #define CONFIG_PCIE3 /* PCIE controller 3 */
  412. #define CONFIG_PCIE4 /* PCIE controller 4 */
  413. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  414. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  415. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  416. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  417. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  418. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  419. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  420. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  421. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  422. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  423. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  424. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  425. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  426. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  427. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  428. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  429. /* controller 4, Base address 203000 */
  430. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  431. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  432. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  433. #ifdef CONFIG_PCI
  434. #if !defined(CONFIG_DM_PCI)
  435. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  436. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  437. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  438. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  439. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  440. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  441. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  442. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  443. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  444. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  445. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  446. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  447. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  448. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  449. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  450. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  451. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  452. #define CONFIG_PCI_INDIRECT_BRIDGE
  453. #endif
  454. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  455. #endif
  456. /* Qman/Bman */
  457. #ifndef CONFIG_NOBQFMAN
  458. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  459. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  460. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  461. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  462. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  463. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  464. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  465. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  466. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  467. CONFIG_SYS_BMAN_CENA_SIZE)
  468. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  469. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  470. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  471. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  472. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  473. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  474. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  475. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  476. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  477. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  478. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  479. CONFIG_SYS_QMAN_CENA_SIZE)
  480. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  481. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  482. #define CONFIG_SYS_DPAA_FMAN
  483. #define CONFIG_SYS_DPAA_PME
  484. #define CONFIG_SYS_PMAN
  485. #define CONFIG_SYS_DPAA_DCE
  486. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  487. #define CONFIG_SYS_INTERLAKEN
  488. /* Default address of microcode for the Linux Fman driver */
  489. #if defined(CONFIG_SPIFLASH)
  490. /*
  491. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  492. * env, so we got 0x110000.
  493. */
  494. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  495. #elif defined(CONFIG_SDCARD)
  496. /*
  497. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  498. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  499. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  500. */
  501. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  502. #elif defined(CONFIG_MTD_RAW_NAND)
  503. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  504. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  505. /*
  506. * Slave has no ucode locally, it can fetch this from remote. When implementing
  507. * in two corenet boards, slave's ucode could be stored in master's memory
  508. * space, the address can be mapped from slave TLB->slave LAW->
  509. * slave SRIO or PCIE outbound window->master inbound window->
  510. * master LAW->the ucode address in master's memory space.
  511. */
  512. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  513. #else
  514. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  515. #endif
  516. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  517. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  518. #endif /* CONFIG_NOBQFMAN */
  519. #ifdef CONFIG_SYS_DPAA_FMAN
  520. #define RGMII_PHY1_ADDR 0x1
  521. #define RGMII_PHY2_ADDR 0x2
  522. #define FM1_10GEC1_PHY_ADDR 0x3
  523. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  524. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  525. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  526. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  527. #endif
  528. #ifdef CONFIG_FMAN_ENET
  529. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  530. #endif
  531. /*
  532. * SATA
  533. */
  534. #ifdef CONFIG_FSL_SATA_V2
  535. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  536. #define CONFIG_SATA1
  537. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  538. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  539. #define CONFIG_SATA2
  540. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  541. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  542. #define CONFIG_LBA48
  543. #endif
  544. /*
  545. * USB
  546. */
  547. #ifdef CONFIG_USB_EHCI_HCD
  548. #define CONFIG_USB_EHCI_FSL
  549. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  550. #define CONFIG_HAS_FSL_DR_USB
  551. #endif
  552. /*
  553. * SDHC
  554. */
  555. #ifdef CONFIG_MMC
  556. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  557. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  558. #endif
  559. /*
  560. * Dynamic MTD Partition support with mtdparts
  561. */
  562. /*
  563. * Environment
  564. */
  565. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  566. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  567. /*
  568. * Miscellaneous configurable options
  569. */
  570. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  571. /*
  572. * For booting Linux, the board info and command line data
  573. * have to be in the first 64 MB of memory, since this is
  574. * the maximum mapped by the Linux kernel during initialization.
  575. */
  576. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  577. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  578. #ifdef CONFIG_CMD_KGDB
  579. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  580. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  581. #endif
  582. /*
  583. * Environment Configuration
  584. */
  585. #define CONFIG_ROOTPATH "/opt/nfsroot"
  586. #define CONFIG_BOOTFILE "uImage"
  587. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  588. /* default location for tftp and bootm */
  589. #define CONFIG_LOADADDR 1000000
  590. #define __USB_PHY_TYPE utmi
  591. #define CONFIG_EXTRA_ENV_SETTINGS \
  592. "hwconfig=fsl_ddr:" \
  593. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  594. "bank_intlv=auto;" \
  595. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  596. "netdev=eth0\0" \
  597. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  598. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  599. "tftpflash=tftpboot $loadaddr $uboot && " \
  600. "protect off $ubootaddr +$filesize && " \
  601. "erase $ubootaddr +$filesize && " \
  602. "cp.b $loadaddr $ubootaddr $filesize && " \
  603. "protect on $ubootaddr +$filesize && " \
  604. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  605. "consoledev=ttyS0\0" \
  606. "ramdiskaddr=2000000\0" \
  607. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  608. "fdtaddr=1e00000\0" \
  609. "fdtfile=t2080qds/t2080qds.dtb\0" \
  610. "bdev=sda3\0"
  611. /*
  612. * For emulation this causes u-boot to jump to the start of the
  613. * proof point app code automatically
  614. */
  615. #define CONFIG_PROOF_POINTS \
  616. "setenv bootargs root=/dev/$bdev rw " \
  617. "console=$consoledev,$baudrate $othbootargs;" \
  618. "cpu 1 release 0x29000000 - - -;" \
  619. "cpu 2 release 0x29000000 - - -;" \
  620. "cpu 3 release 0x29000000 - - -;" \
  621. "cpu 4 release 0x29000000 - - -;" \
  622. "cpu 5 release 0x29000000 - - -;" \
  623. "cpu 6 release 0x29000000 - - -;" \
  624. "cpu 7 release 0x29000000 - - -;" \
  625. "go 0x29000000"
  626. #define CONFIG_HVBOOT \
  627. "setenv bootargs config-addr=0x60000000; " \
  628. "bootm 0x01000000 - 0x00f00000"
  629. #define CONFIG_ALU \
  630. "setenv bootargs root=/dev/$bdev rw " \
  631. "console=$consoledev,$baudrate $othbootargs;" \
  632. "cpu 1 release 0x01000000 - - -;" \
  633. "cpu 2 release 0x01000000 - - -;" \
  634. "cpu 3 release 0x01000000 - - -;" \
  635. "cpu 4 release 0x01000000 - - -;" \
  636. "cpu 5 release 0x01000000 - - -;" \
  637. "cpu 6 release 0x01000000 - - -;" \
  638. "cpu 7 release 0x01000000 - - -;" \
  639. "go 0x01000000"
  640. #define CONFIG_LINUX \
  641. "setenv bootargs root=/dev/ram rw " \
  642. "console=$consoledev,$baudrate $othbootargs;" \
  643. "setenv ramdiskaddr 0x02000000;" \
  644. "setenv fdtaddr 0x00c00000;" \
  645. "setenv loadaddr 0x1000000;" \
  646. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  647. #define CONFIG_HDBOOT \
  648. "setenv bootargs root=/dev/$bdev rw " \
  649. "console=$consoledev,$baudrate $othbootargs;" \
  650. "tftp $loadaddr $bootfile;" \
  651. "tftp $fdtaddr $fdtfile;" \
  652. "bootm $loadaddr - $fdtaddr"
  653. #define CONFIG_NFSBOOTCOMMAND \
  654. "setenv bootargs root=/dev/nfs rw " \
  655. "nfsroot=$serverip:$rootpath " \
  656. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  657. "console=$consoledev,$baudrate $othbootargs;" \
  658. "tftp $loadaddr $bootfile;" \
  659. "tftp $fdtaddr $fdtfile;" \
  660. "bootm $loadaddr - $fdtaddr"
  661. #define CONFIG_RAMBOOTCOMMAND \
  662. "setenv bootargs root=/dev/ram rw " \
  663. "console=$consoledev,$baudrate $othbootargs;" \
  664. "tftp $ramdiskaddr $ramdiskfile;" \
  665. "tftp $loadaddr $bootfile;" \
  666. "tftp $fdtaddr $fdtfile;" \
  667. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  668. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  669. #include <asm/fsl_secure_boot.h>
  670. #endif /* __T208xQDS_H */