P2041RDB.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * P2041 RDB board configuration file
  8. * Also supports P2040 RDB
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. #ifdef CONFIG_RAMBOOT_PBL
  13. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  15. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  16. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  17. #endif
  18. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  19. /* Set 1M boot space */
  20. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  21. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  22. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #endif
  25. /* High Level Configuration Options */
  26. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  27. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  28. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  29. #endif
  30. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  31. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  32. #define CONFIG_PCIE1 /* PCIE controller 1 */
  33. #define CONFIG_PCIE2 /* PCIE controller 2 */
  34. #define CONFIG_PCIE3 /* PCIE controller 3 */
  35. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  36. #define CONFIG_SYS_SRIO
  37. #define CONFIG_SRIO1 /* SRIO port 1 */
  38. #define CONFIG_SRIO2 /* SRIO port 2 */
  39. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  40. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  41. #if defined(CONFIG_SPIFLASH)
  42. #elif defined(CONFIG_SDCARD)
  43. #define CONFIG_FSL_FIXED_MMC_LOCATION
  44. #endif
  45. #ifndef __ASSEMBLY__
  46. unsigned long get_board_sys_clk(unsigned long dummy);
  47. #include <linux/stringify.h>
  48. #endif
  49. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  50. /*
  51. * These can be toggled for performance analysis, otherwise use default.
  52. */
  53. #define CONFIG_SYS_CACHE_STASHING
  54. #define CONFIG_BACKSIDE_L2_CACHE
  55. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  56. #define CONFIG_BTB /* toggle branch predition */
  57. #define CONFIG_ENABLE_36BIT_PHYS
  58. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  59. /*
  60. * Config the L3 Cache as L3 SRAM
  61. */
  62. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  63. #ifdef CONFIG_PHYS_64BIT
  64. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  65. CONFIG_RAMBOOT_TEXT_BASE)
  66. #else
  67. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  68. #endif
  69. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  70. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  71. #ifdef CONFIG_PHYS_64BIT
  72. #define CONFIG_SYS_DCSRBAR 0xf0000000
  73. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  74. #endif
  75. /* EEPROM */
  76. #define CONFIG_ID_EEPROM
  77. #define CONFIG_SYS_I2C_EEPROM_NXID
  78. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  79. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  80. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  81. /*
  82. * DDR Setup
  83. */
  84. #define CONFIG_VERY_BIG_RAM
  85. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  86. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  87. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  88. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  89. #define CONFIG_DDR_SPD
  90. #define CONFIG_SYS_SPD_BUS_NUM 0
  91. #define SPD_EEPROM_ADDRESS 0x52
  92. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  93. /*
  94. * Local Bus Definitions
  95. */
  96. /* Set the local bus clock 1/8 of platform clock */
  97. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  98. /*
  99. * This board doesn't have a promjet connector.
  100. * However, it uses commone corenet board LAW and TLB.
  101. * It is necessary to use the same start address with proper offset.
  102. */
  103. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  104. #ifdef CONFIG_PHYS_64BIT
  105. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  106. #else
  107. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  108. #endif
  109. #define CONFIG_SYS_FLASH_BR_PRELIM \
  110. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
  111. BR_PS_16 | BR_V)
  112. #define CONFIG_SYS_FLASH_OR_PRELIM \
  113. ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  114. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  115. #define CONFIG_FSL_CPLD
  116. #define CPLD_BASE 0xffdf0000 /* CPLD registers */
  117. #ifdef CONFIG_PHYS_64BIT
  118. #define CPLD_BASE_PHYS 0xfffdf0000ull
  119. #else
  120. #define CPLD_BASE_PHYS CPLD_BASE
  121. #endif
  122. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
  123. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  124. #define PIXIS_LBMAP_SWITCH 7
  125. #define PIXIS_LBMAP_MASK 0xf0
  126. #define PIXIS_LBMAP_SHIFT 4
  127. #define PIXIS_LBMAP_ALTBANK 0x40
  128. #define CONFIG_SYS_FLASH_QUIET_TEST
  129. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  130. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  132. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
  133. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
  134. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  135. #if defined(CONFIG_RAMBOOT_PBL)
  136. #define CONFIG_SYS_RAMBOOT
  137. #endif
  138. #define CONFIG_NAND_FSL_ELBC
  139. /* Nand Flash */
  140. #ifdef CONFIG_NAND_FSL_ELBC
  141. #define CONFIG_SYS_NAND_BASE 0xffa00000
  142. #ifdef CONFIG_PHYS_64BIT
  143. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  144. #else
  145. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  146. #endif
  147. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  148. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  149. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  150. /* NAND flash config */
  151. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  152. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  153. | BR_PS_8 /* Port Size = 8 bit */ \
  154. | BR_MS_FCM /* MSEL = FCM */ \
  155. | BR_V) /* valid */
  156. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  157. | OR_FCM_PGS /* Large Page*/ \
  158. | OR_FCM_CSCT \
  159. | OR_FCM_CST \
  160. | OR_FCM_CHT \
  161. | OR_FCM_SCY_1 \
  162. | OR_FCM_TRLX \
  163. | OR_FCM_EHTR)
  164. #ifdef CONFIG_MTD_RAW_NAND
  165. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  166. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  167. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  168. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  169. #else
  170. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  171. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  172. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  173. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  174. #endif
  175. #else
  176. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  177. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  178. #endif /* CONFIG_NAND_FSL_ELBC */
  179. #define CONFIG_SYS_FLASH_EMPTY_INFO
  180. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  181. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  182. #define CONFIG_HWCONFIG
  183. /* define to use L1 as initial stack */
  184. #define CONFIG_L1_INIT_RAM
  185. #define CONFIG_SYS_INIT_RAM_LOCK
  186. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  187. #ifdef CONFIG_PHYS_64BIT
  188. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  189. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  190. /* The assembler doesn't like typecast */
  191. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  192. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  193. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  194. #else
  195. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  196. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  197. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  198. #endif
  199. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  200. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  201. GENERATED_GBL_DATA_SIZE)
  202. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  203. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  204. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  205. /* Serial Port - controlled on board with jumper J8
  206. * open - index 2
  207. * shorted - index 1
  208. */
  209. #define CONFIG_SYS_NS16550_SERIAL
  210. #define CONFIG_SYS_NS16550_REG_SIZE 1
  211. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  212. #define CONFIG_SYS_BAUDRATE_TABLE \
  213. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  214. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  215. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  216. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  217. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  218. /* I2C */
  219. #if !CONFIG_IS_ENABLED(DM_I2C)
  220. #define CONFIG_SYS_I2C_LEGACY
  221. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  222. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  223. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  224. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  225. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  226. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  227. #else
  228. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  229. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  230. #endif
  231. #define CONFIG_SYS_I2C_FSL
  232. /*
  233. * RapidIO
  234. */
  235. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  236. #ifdef CONFIG_PHYS_64BIT
  237. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  238. #else
  239. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  240. #endif
  241. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  242. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  243. #ifdef CONFIG_PHYS_64BIT
  244. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  245. #else
  246. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  247. #endif
  248. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  249. /*
  250. * for slave u-boot IMAGE instored in master memory space,
  251. * PHYS must be aligned based on the SIZE
  252. */
  253. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  254. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  255. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  256. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  257. /*
  258. * for slave UCODE and ENV instored in master memory space,
  259. * PHYS must be aligned based on the SIZE
  260. */
  261. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  262. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  263. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  264. /* slave core release by master*/
  265. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  266. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  267. /*
  268. * SRIO_PCIE_BOOT - SLAVE
  269. */
  270. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  271. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  272. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  273. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  274. #endif
  275. /*
  276. * eSPI - Enhanced SPI
  277. */
  278. /*
  279. * General PCI
  280. * Memory space is mapped 1-1, but I/O space must start from 0.
  281. */
  282. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  283. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  284. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  285. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  286. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  287. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  288. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  289. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  290. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  291. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  292. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  293. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  294. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  295. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  296. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  297. /* Qman/Bman */
  298. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  299. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  300. #ifdef CONFIG_PHYS_64BIT
  301. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  302. #else
  303. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  304. #endif
  305. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  306. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  307. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  308. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  309. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  310. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  311. CONFIG_SYS_BMAN_CENA_SIZE)
  312. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  313. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  314. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  315. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  316. #ifdef CONFIG_PHYS_64BIT
  317. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  318. #else
  319. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  320. #endif
  321. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  322. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  323. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  324. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  325. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  326. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  327. CONFIG_SYS_QMAN_CENA_SIZE)
  328. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  329. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  330. #define CONFIG_SYS_DPAA_FMAN
  331. #define CONFIG_SYS_DPAA_PME
  332. /* Default address of microcode for the Linux Fman driver */
  333. #if defined(CONFIG_SPIFLASH)
  334. /*
  335. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  336. * env, so we got 0x110000.
  337. */
  338. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  339. #elif defined(CONFIG_SDCARD)
  340. /*
  341. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  342. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  343. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  344. */
  345. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  346. #elif defined(CONFIG_MTD_RAW_NAND)
  347. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  348. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  349. /*
  350. * Slave has no ucode locally, it can fetch this from remote. When implementing
  351. * in two corenet boards, slave's ucode could be stored in master's memory
  352. * space, the address can be mapped from slave TLB->slave LAW->
  353. * slave SRIO or PCIE outbound window->master inbound window->
  354. * master LAW->the ucode address in master's memory space.
  355. */
  356. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  357. #else
  358. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  359. #endif
  360. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  361. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  362. #ifdef CONFIG_PCI
  363. #if !defined(CONFIG_DM_PCI)
  364. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  365. #define CONFIG_PCI_INDIRECT_BRIDGE
  366. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  367. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  368. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  369. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  370. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  371. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  372. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  373. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  374. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  375. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  376. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  377. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  378. #endif
  379. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  380. #endif /* CONFIG_PCI */
  381. /* SATA */
  382. #define CONFIG_FSL_SATA_V2
  383. #ifdef CONFIG_FSL_SATA_V2
  384. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  385. #define CONFIG_SATA1
  386. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  387. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  388. #define CONFIG_SATA2
  389. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  390. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  391. #define CONFIG_LBA48
  392. #endif
  393. #ifdef CONFIG_FMAN_ENET
  394. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
  395. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
  396. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
  397. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
  398. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
  399. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  400. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  401. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  402. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  403. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
  404. #define CONFIG_SYS_TBIPA_VALUE 8
  405. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  406. #endif
  407. /*
  408. * Environment
  409. */
  410. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  411. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  412. /*
  413. * USB
  414. */
  415. #define CONFIG_HAS_FSL_DR_USB
  416. #define CONFIG_HAS_FSL_MPH_USB
  417. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  418. #define CONFIG_USB_EHCI_FSL
  419. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  420. #endif
  421. #ifdef CONFIG_MMC
  422. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  423. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  424. #endif
  425. /*
  426. * Miscellaneous configurable options
  427. */
  428. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  429. /*
  430. * For booting Linux, the board info and command line data
  431. * have to be in the first 64 MB of memory, since this is
  432. * the maximum mapped by the Linux kernel during initialization.
  433. */
  434. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  435. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  436. #ifdef CONFIG_CMD_KGDB
  437. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  438. #endif
  439. /*
  440. * Environment Configuration
  441. */
  442. #define CONFIG_ROOTPATH "/opt/nfsroot"
  443. #define CONFIG_BOOTFILE "uImage"
  444. #define CONFIG_UBOOTPATH u-boot.bin
  445. /* default location for tftp and bootm */
  446. #define CONFIG_LOADADDR 1000000
  447. #define __USB_PHY_TYPE utmi
  448. #define CONFIG_EXTRA_ENV_SETTINGS \
  449. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  450. "bank_intlv=cs0_cs1\0" \
  451. "netdev=eth0\0" \
  452. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  453. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  454. "tftpflash=tftpboot $loadaddr $uboot && " \
  455. "protect off $ubootaddr +$filesize && " \
  456. "erase $ubootaddr +$filesize && " \
  457. "cp.b $loadaddr $ubootaddr $filesize && " \
  458. "protect on $ubootaddr +$filesize && " \
  459. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  460. "consoledev=ttyS0\0" \
  461. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  462. "usb_dr_mode=host\0" \
  463. "ramdiskaddr=2000000\0" \
  464. "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
  465. "fdtaddr=1e00000\0" \
  466. "fdtfile=p2041rdb/p2041rdb.dtb\0" \
  467. "bdev=sda3\0"
  468. #define CONFIG_HDBOOT \
  469. "setenv bootargs root=/dev/$bdev rw " \
  470. "console=$consoledev,$baudrate $othbootargs;" \
  471. "tftp $loadaddr $bootfile;" \
  472. "tftp $fdtaddr $fdtfile;" \
  473. "bootm $loadaddr - $fdtaddr"
  474. #define CONFIG_NFSBOOTCOMMAND \
  475. "setenv bootargs root=/dev/nfs rw " \
  476. "nfsroot=$serverip:$rootpath " \
  477. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  478. "console=$consoledev,$baudrate $othbootargs;" \
  479. "tftp $loadaddr $bootfile;" \
  480. "tftp $fdtaddr $fdtfile;" \
  481. "bootm $loadaddr - $fdtaddr"
  482. #define CONFIG_RAMBOOTCOMMAND \
  483. "setenv bootargs root=/dev/ram rw " \
  484. "console=$consoledev,$baudrate $othbootargs;" \
  485. "tftp $ramdiskaddr $ramdiskfile;" \
  486. "tftp $loadaddr $bootfile;" \
  487. "tftp $fdtaddr $fdtfile;" \
  488. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  489. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  490. #include <asm/fsl_secure_boot.h>
  491. #endif /* __CONFIG_H */