M53017EVB.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF53017EVB.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M53017EVB_H
  12. #define _M53017EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000
  21. #define CONFIG_SYS_UNIFY_CACHE
  22. #ifdef CONFIG_MCFFEC
  23. # define CONFIG_MII_INIT 1
  24. # define CONFIG_SYS_DISCOVER_PHY
  25. # define CONFIG_SYS_RX_ETH_BUFFER 8
  26. # define CONFIG_SYS_TX_ETH_BUFFER 8
  27. # define CONFIG_SYS_FEC_BUF_USE_SRAM
  28. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  29. # define CONFIG_HAS_ETH1
  30. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  31. # ifndef CONFIG_SYS_DISCOVER_PHY
  32. # define FECDUPLEX FULL
  33. # define FECSPEED _100BASET
  34. # else
  35. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  37. # endif
  38. # endif /* CONFIG_SYS_DISCOVER_PHY */
  39. #endif
  40. #define CONFIG_MCFRTC
  41. #undef RTC_DEBUG
  42. #define CONFIG_SYS_RTC_CNT (0x8000)
  43. #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  44. /* Timer */
  45. #define CONFIG_MCFTMR
  46. /* I2C */
  47. #define CONFIG_SYS_I2C_LEGACY
  48. #define CONFIG_SYS_I2C_FSL
  49. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  50. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  51. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  52. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  53. #define CONFIG_UDP_CHECKSUM
  54. #ifdef CONFIG_MCFFEC
  55. # define CONFIG_IPADDR 192.162.1.2
  56. # define CONFIG_NETMASK 255.255.255.0
  57. # define CONFIG_SERVERIP 192.162.1.1
  58. # define CONFIG_GATEWAYIP 192.162.1.1
  59. #endif /* FEC_ENET */
  60. #define CONFIG_HOSTNAME "M53017"
  61. #define CONFIG_EXTRA_ENV_SETTINGS \
  62. "netdev=eth0\0" \
  63. "loadaddr=40010000\0" \
  64. "u-boot=u-boot.bin\0" \
  65. "load=tftp ${loadaddr) ${u-boot}\0" \
  66. "upd=run load; run prog\0" \
  67. "prog=prot off 0 3ffff;" \
  68. "era 0 3ffff;" \
  69. "cp.b ${loadaddr} 0 ${filesize};" \
  70. "save\0" \
  71. ""
  72. #define CONFIG_PRAM 512 /* 512 KB */
  73. #define CONFIG_SYS_LOAD_ADDR 0x40010000
  74. #define CONFIG_SYS_CLK 80000000
  75. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
  76. #define CONFIG_SYS_MBAR 0xFC000000
  77. /*
  78. * Low Level Configuration Settings
  79. * (address mappings, register initial values, etc.)
  80. * You should know what you are doing if you make changes here.
  81. */
  82. /*
  83. * Definitions for initial stack pointer and data area (in DPRAM)
  84. */
  85. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  86. #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
  87. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  88. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  89. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  90. /*
  91. * Start addresses for the final memory configuration
  92. * (Set up by the startup code)
  93. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  94. */
  95. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  96. #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
  97. #define CONFIG_SYS_SDRAM_CFG1 0x43711630
  98. #define CONFIG_SYS_SDRAM_CFG2 0x56670000
  99. #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
  100. #define CONFIG_SYS_SDRAM_EMOD 0x80010000
  101. #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
  102. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  103. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  104. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  105. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  106. /*
  107. * For booting Linux, the board info and command line data
  108. * have to be in the first 8 MB of memory, since this is
  109. * the maximum mapped by the Linux kernel during initialization ??
  110. */
  111. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  112. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  113. /*-----------------------------------------------------------------------
  114. * FLASH organization
  115. */
  116. #ifdef CONFIG_SYS_FLASH_CFI
  117. # define CONFIG_FLASH_SPANSION_S29WS_N 1
  118. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  119. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  120. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  121. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  122. #endif
  123. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  124. /* Configuration for environment
  125. * Environment is embedded in u-boot in the second sector of the flash
  126. */
  127. #define LDS_BOARD_TEXT \
  128. . = DEFINED(env_offset) ? env_offset : .; \
  129. env/embedded.o(.text*)
  130. /*-----------------------------------------------------------------------
  131. * Cache Configuration
  132. */
  133. #define CONFIG_SYS_CACHELINE_SIZE 16
  134. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  135. CONFIG_SYS_INIT_RAM_SIZE - 8)
  136. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  137. CONFIG_SYS_INIT_RAM_SIZE - 4)
  138. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
  139. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  140. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  141. CF_ACR_EN | CF_ACR_SM_ALL)
  142. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
  143. CF_CACR_DCM_P)
  144. /*-----------------------------------------------------------------------
  145. * Chipselect bank definitions
  146. */
  147. /*
  148. * CS0 - NOR Flash
  149. * CS1 - Ext SRAM
  150. * CS2 - Available
  151. * CS3 - Available
  152. * CS4 - Available
  153. * CS5 - Available
  154. */
  155. #define CONFIG_SYS_CS0_BASE 0
  156. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  157. #define CONFIG_SYS_CS0_CTRL 0x00001FA0
  158. #define CONFIG_SYS_CS1_BASE 0xC0000000
  159. #define CONFIG_SYS_CS1_MASK 0x00070001
  160. #define CONFIG_SYS_CS1_CTRL 0x00001FA0
  161. #endif /* _M53017EVB_H */