tqma6.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
  7. * Author: Markus Niebel <markus.niebel@tq-group.com>
  8. */
  9. #include <init.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <env.h>
  16. #include <fdt_support.h>
  17. #include <asm/global_data.h>
  18. #include <linux/errno.h>
  19. #include <asm/gpio.h>
  20. #include <asm/io.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/mach-imx/spi.h>
  23. #include <common.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <linux/libfdt.h>
  26. #include <i2c.h>
  27. #include <mmc.h>
  28. #include <power/pfuze100_pmic.h>
  29. #include <power/pmic.h>
  30. #include <spi_flash.h>
  31. #include "tqma6_bb.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  34. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39. #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  40. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  41. #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. int dram_init(void)
  47. {
  48. gd->ram_size = imx_ddr_size();
  49. return 0;
  50. }
  51. static const uint16_t tqma6_emmc_dsr = 0x0100;
  52. #ifndef CONFIG_DM_MMC
  53. /* eMMC on USDHCI3 always present */
  54. static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
  55. NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
  56. NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
  57. NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
  58. NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
  59. NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
  60. NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
  61. NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
  62. NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
  63. NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
  64. NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
  65. /* eMMC reset */
  66. NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
  67. };
  68. /*
  69. * According to board_mmc_init() the following map is done:
  70. * (U-Boot device node) (Physical Port)
  71. * mmc0 eMMC (SD3) on TQMa6
  72. * mmc1 .. n optional slots used on baseboard
  73. */
  74. struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
  75. .esdhc_base = USDHC3_BASE_ADDR,
  76. .max_bus_width = 8,
  77. };
  78. int board_mmc_getcd(struct mmc *mmc)
  79. {
  80. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  81. int ret = 0;
  82. if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  83. /* eMMC/uSDHC3 is always present */
  84. ret = 1;
  85. else
  86. ret = tqma6_bb_board_mmc_getcd(mmc);
  87. return ret;
  88. }
  89. int board_mmc_getwp(struct mmc *mmc)
  90. {
  91. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  92. int ret = 0;
  93. if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  94. /* eMMC/uSDHC3 is always present */
  95. ret = 0;
  96. else
  97. ret = tqma6_bb_board_mmc_getwp(mmc);
  98. return ret;
  99. }
  100. int board_mmc_init(struct bd_info *bis)
  101. {
  102. imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
  103. ARRAY_SIZE(tqma6_usdhc3_pads));
  104. tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  105. if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
  106. puts("Warning: failed to initialize eMMC dev\n");
  107. } else {
  108. struct mmc *mmc = find_mmc_device(0);
  109. if (mmc)
  110. mmc_set_dsr(mmc, tqma6_emmc_dsr);
  111. }
  112. tqma6_bb_board_mmc_init(bis);
  113. return 0;
  114. }
  115. #endif
  116. #ifndef CONFIG_DM_SPI
  117. static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
  118. /* SS1 */
  119. NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
  120. NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
  121. NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
  122. NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
  123. };
  124. #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
  125. static unsigned const tqma6_ecspi1_cs[] = {
  126. TQMA6_SF_CS_GPIO,
  127. };
  128. __weak void tqma6_iomuxc_spi(void)
  129. {
  130. unsigned i;
  131. for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
  132. gpio_direction_output(tqma6_ecspi1_cs[i], 1);
  133. imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
  134. ARRAY_SIZE(tqma6_ecspi1_pads));
  135. }
  136. #if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
  137. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  138. {
  139. return ((bus == CONFIG_SF_DEFAULT_BUS) &&
  140. (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
  141. }
  142. #endif
  143. #endif
  144. #ifdef CONFIG_SYS_I2C_LEGACY
  145. static struct i2c_pads_info tqma6_i2c3_pads = {
  146. /* I2C3: on board LM75, M24C64, */
  147. .scl = {
  148. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
  149. I2C_PAD_CTRL),
  150. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
  151. I2C_PAD_CTRL),
  152. .gp = IMX_GPIO_NR(1, 5)
  153. },
  154. .sda = {
  155. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
  156. I2C_PAD_CTRL),
  157. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
  158. I2C_PAD_CTRL),
  159. .gp = IMX_GPIO_NR(1, 6)
  160. }
  161. };
  162. static void tqma6_setup_i2c(void)
  163. {
  164. int ret;
  165. /*
  166. * use logical index for bus, e.g. I2C1 -> 0
  167. * warn on error
  168. */
  169. ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
  170. if (ret)
  171. printf("setup I2C3 failed: %d\n", ret);
  172. }
  173. #endif
  174. int board_early_init_f(void)
  175. {
  176. return tqma6_bb_board_early_init_f();
  177. }
  178. int board_init(void)
  179. {
  180. /* address of boot parameters */
  181. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  182. #ifndef CONFIG_DM_SPI
  183. tqma6_iomuxc_spi();
  184. #endif
  185. #ifdef CONFIG_SYS_I2C_LEGACY
  186. tqma6_setup_i2c();
  187. #endif
  188. tqma6_bb_board_init();
  189. return 0;
  190. }
  191. static const char *tqma6_get_boardname(void)
  192. {
  193. u32 cpurev = get_cpu_rev();
  194. switch ((cpurev & 0xFF000) >> 12) {
  195. case MXC_CPU_MX6SOLO:
  196. return "TQMa6S";
  197. break;
  198. case MXC_CPU_MX6DL:
  199. return "TQMa6DL";
  200. break;
  201. case MXC_CPU_MX6D:
  202. return "TQMa6D";
  203. break;
  204. case MXC_CPU_MX6Q:
  205. return "TQMa6Q";
  206. break;
  207. default:
  208. return "??";
  209. };
  210. }
  211. #ifdef CONFIG_POWER
  212. /* setup board specific PMIC */
  213. int power_init_board(void)
  214. {
  215. struct pmic *p;
  216. u32 reg, rev;
  217. power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
  218. p = pmic_get("PFUZE100");
  219. if (p && !pmic_probe(p)) {
  220. pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  221. pmic_reg_read(p, PFUZE100_REVID, &rev);
  222. printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
  223. }
  224. return 0;
  225. }
  226. #endif
  227. int board_late_init(void)
  228. {
  229. env_set("board_name", tqma6_get_boardname());
  230. tqma6_bb_board_late_init();
  231. return 0;
  232. }
  233. int checkboard(void)
  234. {
  235. printf("Board: %s on a %s\n", tqma6_get_boardname(),
  236. tqma6_bb_get_boardname());
  237. return 0;
  238. }
  239. /*
  240. * Device Tree Support
  241. */
  242. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  243. #define MODELSTRLEN 32u
  244. int ft_board_setup(void *blob, struct bd_info *bd)
  245. {
  246. char modelstr[MODELSTRLEN];
  247. snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
  248. tqma6_bb_get_boardname());
  249. do_fixup_by_path_string(blob, "/", "model", modelstr);
  250. fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
  251. /* bring in eMMC dsr settings */
  252. do_fixup_by_path_u32(blob,
  253. "/soc/aips-bus@02100000/usdhc@02198000",
  254. "dsr", tqma6_emmc_dsr, 2);
  255. tqma6_bb_ft_board_setup(blob, bd);
  256. return 0;
  257. }
  258. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */