visionsom-6ull.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2019 A. Karas, SomLabs
  4. * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  5. */
  6. #include <init.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/global_data.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/io.h>
  19. #include <common.h>
  20. #include <env.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <i2c.h>
  23. #include <miiphy.h>
  24. #include <linux/sizes.h>
  25. #include <mmc.h>
  26. #include <netdev.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  29. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  30. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. int dram_init(void)
  32. {
  33. gd->ram_size = imx_ddr_size();
  34. return 0;
  35. }
  36. static iomux_v3_cfg_t const uart1_pads[] = {
  37. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  38. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  39. };
  40. static void setup_iomux_uart(void)
  41. {
  42. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  43. }
  44. #ifdef CONFIG_FEC_MXC
  45. static int setup_fec(void)
  46. {
  47. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  48. int ret;
  49. /*
  50. * Use 50M anatop loopback REF_CLK1 for ENET1,
  51. * clear gpr1[13], set gpr1[17].
  52. */
  53. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  54. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  55. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  56. if (ret)
  57. return ret;
  58. enable_enet_clk(1);
  59. return 0;
  60. }
  61. int board_phy_config(struct phy_device *phydev)
  62. {
  63. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  64. if (phydev->drv->config)
  65. phydev->drv->config(phydev);
  66. return 0;
  67. }
  68. #endif
  69. int board_mmc_get_env_dev(int devno)
  70. {
  71. return devno;
  72. }
  73. int mmc_map_to_kernel_blk(int devno)
  74. {
  75. return devno;
  76. }
  77. int board_early_init_f(void)
  78. {
  79. setup_iomux_uart();
  80. return 0;
  81. }
  82. int board_init(void)
  83. {
  84. /* Address of boot parameters */
  85. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  86. #ifdef CONFIG_SYS_I2C_LEGACY
  87. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  88. #endif
  89. #ifdef CONFIG_FEC_MXC
  90. setup_fec();
  91. #endif
  92. return 0;
  93. }
  94. #ifdef CONFIG_CMD_BMODE
  95. static const struct boot_mode board_boot_modes[] = {
  96. /* 4 bit bus width */
  97. {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  98. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  99. {NULL, 0},
  100. };
  101. #endif
  102. int board_late_init(void)
  103. {
  104. #ifdef CONFIG_CMD_BMODE
  105. add_board_boot_modes(board_boot_modes);
  106. #endif
  107. if (is_cpu_type(MXC_CPU_MX6ULL))
  108. env_set("board", "visionsom-6ull");
  109. else
  110. env_set("board", "visionsom-6ul");
  111. return 0;
  112. }
  113. int checkboard(void)
  114. {
  115. printf("Board: SoMLabs VisionSOM-6UL%s\n",
  116. is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
  117. return 0;
  118. }