config.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016-2018, 2020 NXP
  4. * Copyright 2015, Freescale Semiconductor
  5. */
  6. #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
  7. #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
  8. #include <linux/kconfig.h>
  9. #include <fsl_ddrc_version.h>
  10. #ifndef __ASSEMBLY__
  11. #include <linux/bitops.h>
  12. #endif
  13. #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
  14. /*
  15. * Reserve secure memory
  16. * To be aligned with MMU block size
  17. */
  18. #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
  19. #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
  20. #ifdef CONFIG_ARCH_LS2080A
  21. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
  22. #define SRDS_MAX_LANES 8
  23. #define CONFIG_SYS_PAGE_SIZE 0x10000
  24. #ifndef L1_CACHE_BYTES
  25. #define L1_CACHE_SHIFT 6
  26. #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
  27. #endif
  28. #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  29. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  30. #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  31. /* DDR */
  32. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  33. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  34. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  35. #define CONFIG_SYS_FSL_CCSR_SCFG_LE
  36. #define CONFIG_SYS_FSL_ESDHC_LE
  37. #define CONFIG_SYS_FSL_IFC_LE
  38. #define CONFIG_SYS_FSL_PEX_LUT_LE
  39. #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  40. /* Generic Interrupt Controller Definitions */
  41. #define GICD_BASE 0x06000000
  42. #define GICR_BASE 0x06100000
  43. /* SMMU Defintions */
  44. #define SMMU_BASE 0x05000000 /* GR0 Base */
  45. /* SFP */
  46. #define CONFIG_SYS_FSL_SFP_VER_3_4
  47. #define CONFIG_SYS_FSL_SFP_LE
  48. #define CONFIG_SYS_FSL_SRK_LE
  49. /* Security Monitor */
  50. #define CONFIG_SYS_FSL_SEC_MON_LE
  51. /* Secure Boot */
  52. #define CONFIG_ESBC_HDR_LS
  53. /* DCFG - GUR */
  54. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  55. /* Cache Coherent Interconnect */
  56. #define CCI_MN_BASE 0x04000000
  57. #define CCI_MN_RNF_NODEID_LIST 0x180
  58. #define CCI_MN_DVM_DOMAIN_CTL 0x200
  59. #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
  60. #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
  61. #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
  62. #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
  63. #define CCN_HN_F_SAM_NODEID_MASK 0x7f
  64. #define CCN_HN_F_SAM_NODEID_DDR0 0x4
  65. #define CCN_HN_F_SAM_NODEID_DDR1 0xe
  66. #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
  67. #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
  68. #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
  69. #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
  70. #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
  71. #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
  72. #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
  73. #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
  74. #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
  75. #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
  76. /* TZ Protection Controller Definitions */
  77. #define TZPC_BASE 0x02200000
  78. #define TZPCR0SIZE_BASE (TZPC_BASE)
  79. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  80. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  81. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  82. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  83. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  84. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  85. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  86. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  87. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  88. #define DCSR_CGACRE5 0x700070914ULL
  89. #define EPU_EPCMPR5 0x700060914ULL
  90. #define EPU_EPCCR5 0x700060814ULL
  91. #define EPU_EPSMCR5 0x700060228ULL
  92. #define EPU_EPECR5 0x700060314ULL
  93. #define EPU_EPCTR5 0x700060a14ULL
  94. #define EPU_EPGCR 0x700060000ULL
  95. #define CONFIG_SYS_FSL_ERRATUM_A008751
  96. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  97. #elif defined(CONFIG_ARCH_LS1088A)
  98. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  99. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  100. #define CONFIG_GICV3
  101. #define CONFIG_SYS_PAGE_SIZE 0x10000
  102. #define SRDS_MAX_LANES 4
  103. #define SRDS_BITS_PER_LANE 4
  104. /* TZ Protection Controller Definitions */
  105. #define TZPC_BASE 0x02200000
  106. #define TZPCR0SIZE_BASE (TZPC_BASE)
  107. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  108. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  109. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  110. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  111. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  112. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  113. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  114. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  115. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  116. /* Generic Interrupt Controller Definitions */
  117. #define GICD_BASE 0x06000000
  118. #define GICR_BASE 0x06100000
  119. /* SMMU Defintions */
  120. #define SMMU_BASE 0x05000000 /* GR0 Base */
  121. /* DDR */
  122. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  123. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  124. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  125. #define CONFIG_SYS_FSL_CCSR_SCFG_LE
  126. #define CONFIG_SYS_FSL_ESDHC_LE
  127. #define CONFIG_SYS_FSL_IFC_LE
  128. #define CONFIG_SYS_FSL_PEX_LUT_LE
  129. #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  130. /* SFP */
  131. #define CONFIG_SYS_FSL_SFP_VER_3_4
  132. #define CONFIG_SYS_FSL_SFP_LE
  133. #define CONFIG_SYS_FSL_SRK_LE
  134. /* Security Monitor */
  135. #define CONFIG_SYS_FSL_SEC_MON_LE
  136. /* Secure Boot */
  137. #define CONFIG_ESBC_HDR_LS
  138. /* DCFG - GUR */
  139. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  140. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  141. #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  142. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  143. #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  144. /* LX2160A/LX2162A Soc Support */
  145. #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  146. #define TZPC_BASE 0x02200000
  147. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  148. #if !CONFIG_IS_ENABLED(DM_I2C)
  149. #define CONFIG_SYS_I2C_LEGACY
  150. #define CONFIG_SYS_I2C_EARLY_INIT
  151. #endif
  152. #define SRDS_MAX_LANES 8
  153. #ifndef L1_CACHE_BYTES
  154. #define L1_CACHE_SHIFT 6
  155. #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
  156. #endif
  157. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
  158. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
  159. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  160. #define CONFIG_SYS_PAGE_SIZE 0x10000
  161. #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  162. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  163. #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
  164. /* DDR */
  165. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  166. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  167. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  168. #define CONFIG_SYS_FSL_CCSR_SCFG_LE
  169. #define CONFIG_SYS_FSL_ESDHC_LE
  170. #define CONFIG_SYS_FSL_PEX_LUT_LE
  171. #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  172. /* Generic Interrupt Controller Definitions */
  173. #define GICD_BASE 0x06000000
  174. #define GICR_BASE 0x06200000
  175. /* SMMU Definitions */
  176. #define SMMU_BASE 0x05000000 /* GR0 Base */
  177. /* SFP */
  178. #define CONFIG_SYS_FSL_SFP_VER_3_4
  179. #define CONFIG_SYS_FSL_SFP_LE
  180. #define CONFIG_SYS_FSL_SRK_LE
  181. /* Security Monitor */
  182. #define CONFIG_SYS_FSL_SEC_MON_LE
  183. /* Secure Boot */
  184. #define CONFIG_ESBC_HDR_LS
  185. /* DCFG - GUR */
  186. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  187. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  188. #elif defined(CONFIG_ARCH_LS1028A)
  189. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  190. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  191. #define CONFIG_GICV3
  192. #define CONFIG_FSL_TZPC_BP147
  193. #define CONFIG_FSL_TZASC_400
  194. /* TZ Protection Controller Definitions */
  195. #define TZPC_BASE 0x02200000
  196. #define TZPCR0SIZE_BASE (TZPC_BASE)
  197. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  198. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  199. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  200. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  201. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  202. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  203. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  204. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  205. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  206. #define SRDS_MAX_LANES 4
  207. #define SRDS_BITS_PER_LANE 4
  208. #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  209. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
  210. #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
  211. /* Generic Interrupt Controller Definitions */
  212. #define GICD_BASE 0x06000000
  213. #define GICR_BASE 0x06040000
  214. /* SMMU Definitions */
  215. #define SMMU_BASE 0x05000000 /* GR0 Base */
  216. /* DDR */
  217. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  218. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  219. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  220. #define CONFIG_SYS_FSL_CCSR_SCFG_LE
  221. #define CONFIG_SYS_FSL_ESDHC_LE
  222. #define CONFIG_SYS_FSL_PEX_LUT_LE
  223. #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  224. /* SFP */
  225. #define CONFIG_SYS_FSL_SFP_VER_3_4
  226. #define CONFIG_SYS_FSL_SFP_LE
  227. #define CONFIG_SYS_FSL_SRK_LE
  228. /* SEC */
  229. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  230. /* Security Monitor */
  231. #define CONFIG_SYS_FSL_SEC_MON_LE
  232. /* Secure Boot */
  233. #define CONFIG_ESBC_HDR_LS
  234. /* DCFG - GUR */
  235. #define CONFIG_SYS_FSL_CCSR_GUR_LE
  236. #elif defined(CONFIG_FSL_LSCH2)
  237. #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
  238. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  239. #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  240. #define DCSR_DCFG_SBEESR2 0x20140534
  241. #define DCSR_DCFG_MBEESR2 0x20140544
  242. #define CONFIG_SYS_FSL_CCSR_SCFG_BE
  243. #define CONFIG_SYS_FSL_ESDHC_BE
  244. #define CONFIG_SYS_FSL_WDOG_BE
  245. #define CONFIG_SYS_FSL_DSPI_BE
  246. #define CONFIG_SYS_FSL_CCSR_GUR_BE
  247. #define CONFIG_SYS_FSL_PEX_LUT_BE
  248. /* SoC related */
  249. #ifdef CONFIG_ARCH_LS1043A
  250. #define CONFIG_SYS_FMAN_V3
  251. #define CONFIG_SYS_FSL_QMAN_V3
  252. #define CONFIG_SYS_NUM_FMAN 1
  253. #define CONFIG_SYS_NUM_FM1_DTSEC 7
  254. #define CONFIG_SYS_NUM_FM1_10GEC 1
  255. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  256. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  257. #define QE_MURAM_SIZE 0x6000UL
  258. #define MAX_QE_RISC 1
  259. #define QE_NUM_OF_SNUM 28
  260. #define CONFIG_SYS_FSL_IFC_BE
  261. #define CONFIG_SYS_FSL_SFP_VER_3_2
  262. #define CONFIG_SYS_FSL_SEC_MON_BE
  263. #define CONFIG_SYS_FSL_SFP_BE
  264. #define CONFIG_SYS_FSL_SRK_LE
  265. #define CONFIG_KEY_REVOCATION
  266. /* SMMU Defintions */
  267. #define SMMU_BASE 0x09000000
  268. /* Generic Interrupt Controller Definitions */
  269. #define GICD_BASE 0x01401000
  270. #define GICC_BASE 0x01402000
  271. #define GICH_BASE 0x01404000
  272. #define GICV_BASE 0x01406000
  273. #define GICD_SIZE 0x1000
  274. #define GICC_SIZE 0x2000
  275. #define GICH_SIZE 0x2000
  276. #define GICV_SIZE 0x2000
  277. #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
  278. #define GICD_BASE_64K 0x01410000
  279. #define GICC_BASE_64K 0x01420000
  280. #define GICH_BASE_64K 0x01440000
  281. #define GICV_BASE_64K 0x01460000
  282. #define GICD_SIZE_64K 0x10000
  283. #define GICC_SIZE_64K 0x20000
  284. #define GICH_SIZE_64K 0x20000
  285. #define GICV_SIZE_64K 0x20000
  286. #endif
  287. #define DCFG_CCSR_SVR 0x1ee00a4
  288. #define REV1_0 0x10
  289. #define REV1_1 0x11
  290. #define GIC_ADDR_BIT 31
  291. #define SCFG_GIC400_ALIGN 0x1570188
  292. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  293. #elif defined(CONFIG_ARCH_LS1012A)
  294. #define GICD_BASE 0x01401000
  295. #define GICC_BASE 0x01402000
  296. #define CONFIG_SYS_FSL_SFP_VER_3_2
  297. #define CONFIG_SYS_FSL_SEC_MON_BE
  298. #define CONFIG_SYS_FSL_SFP_BE
  299. #define CONFIG_SYS_FSL_SRK_LE
  300. #define CONFIG_KEY_REVOCATION
  301. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  302. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  303. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  304. #elif defined(CONFIG_ARCH_LS1046A)
  305. #define CONFIG_SYS_FMAN_V3
  306. #define CONFIG_SYS_FSL_QMAN_V3
  307. #define CONFIG_SYS_NUM_FMAN 1
  308. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  309. #define CONFIG_SYS_NUM_FM1_10GEC 2
  310. #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  311. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
  312. #define CONFIG_SYS_FSL_IFC_BE
  313. #define CONFIG_SYS_FSL_SFP_VER_3_2
  314. #define CONFIG_SYS_FSL_SEC_MON_BE
  315. #define CONFIG_SYS_FSL_SFP_BE
  316. #define CONFIG_SYS_FSL_SRK_LE
  317. #define CONFIG_KEY_REVOCATION
  318. /* SMMU Defintions */
  319. #define SMMU_BASE 0x09000000
  320. /* Generic Interrupt Controller Definitions */
  321. #define GICD_BASE 0x01410000
  322. #define GICC_BASE 0x01420000
  323. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  324. #else
  325. #error SoC not defined
  326. #endif
  327. #endif
  328. #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */