timer.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * Copyright (C) Marvell International Ltd. and its affiliates
  7. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #define UBOOT_CNTR 0 /* counter to use for uboot timer */
  14. /* Timer reload and current value registers */
  15. struct orion5x_tmr_val {
  16. u32 reload; /* Timer reload reg */
  17. u32 val; /* Timer value reg */
  18. };
  19. /* Timer registers */
  20. struct orion5x_tmr_registers {
  21. u32 ctrl; /* Timer control reg */
  22. u32 pad[3];
  23. struct orion5x_tmr_val tmr[2];
  24. u32 wdt_reload;
  25. u32 wdt_val;
  26. };
  27. struct orion5x_tmr_registers *orion5x_tmr_regs =
  28. (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
  29. /*
  30. * ARM Timers Registers Map
  31. */
  32. #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
  33. #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
  34. #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
  35. /*
  36. * ARM Timers Control Register
  37. * CPU_TIMERS_CTRL_REG (CTCR)
  38. */
  39. #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
  40. #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
  41. #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  42. #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  43. #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
  44. #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
  45. #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  46. #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  47. /*
  48. * ARM Timer\Watchdog Reload Register
  49. * CNTMR_RELOAD_REG (TRR)
  50. */
  51. #define TRG_ARM_TIMER_REL_OFFS 0
  52. #define TRG_ARM_TIMER_REL_MASK 0xffffffff
  53. /*
  54. * ARM Timer\Watchdog Register
  55. * CNTMR_VAL_REG (TVRG)
  56. */
  57. #define TVR_ARM_TIMER_OFFS 0
  58. #define TVR_ARM_TIMER_MASK 0xffffffff
  59. #define TVR_ARM_TIMER_MAX 0xffffffff
  60. #define TIMER_LOAD_VAL 0xffffffff
  61. static inline ulong read_timer(void)
  62. {
  63. return readl(CNTMR_VAL_REG(UBOOT_CNTR))
  64. / (CONFIG_SYS_TCLK / 1000);
  65. }
  66. DECLARE_GLOBAL_DATA_PTR;
  67. #define timestamp gd->arch.tbl
  68. #define lastdec gd->arch.lastinc
  69. static ulong get_timer_masked(void)
  70. {
  71. ulong now = read_timer();
  72. if (lastdec >= now) {
  73. /* normal mode */
  74. timestamp += lastdec - now;
  75. } else {
  76. /* we have an overflow ... */
  77. timestamp += lastdec +
  78. (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  79. }
  80. lastdec = now;
  81. return timestamp;
  82. }
  83. ulong get_timer(ulong base)
  84. {
  85. return get_timer_masked() - base;
  86. }
  87. static inline ulong uboot_cntr_val(void)
  88. {
  89. return readl(CNTMR_VAL_REG(UBOOT_CNTR));
  90. }
  91. void __udelay(unsigned long usec)
  92. {
  93. uint current;
  94. ulong delayticks;
  95. current = uboot_cntr_val();
  96. delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
  97. if (current < delayticks) {
  98. delayticks -= current;
  99. while (uboot_cntr_val() < current)
  100. ;
  101. while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
  102. ;
  103. } else {
  104. while (uboot_cntr_val() > (current - delayticks))
  105. ;
  106. }
  107. }
  108. /*
  109. * init the counter
  110. */
  111. int timer_init(void)
  112. {
  113. unsigned int cntmrctrl;
  114. /* load value into timer */
  115. writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
  116. writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
  117. /* enable timer in auto reload mode */
  118. cntmrctrl = readl(CNTMR_CTRL_REG);
  119. cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
  120. cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
  121. writel(cntmrctrl, CNTMR_CTRL_REG);
  122. return 0;
  123. }
  124. void timer_init_r(void)
  125. {
  126. /* init the timestamp and lastdec value */
  127. lastdec = read_timer();
  128. timestamp = 0;
  129. }
  130. /*
  131. * This function is derived from PowerPC code (read timebase as long long).
  132. * On ARM it just returns the timer value.
  133. */
  134. unsigned long long get_ticks(void)
  135. {
  136. return get_timer(0);
  137. }
  138. /*
  139. * This function is derived from PowerPC code (timebase clock frequency).
  140. * On ARM it returns the number of timer ticks per second.
  141. */
  142. ulong get_tbclk(void)
  143. {
  144. return (ulong)CONFIG_SYS_HZ;
  145. }