sdrc.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Functions related to OMAP3 SDRC.
  4. *
  5. * This file has been created after exctracting and consolidating
  6. * the SDRC related content from mem.c and board.c, also created
  7. * generic init function (mem_init).
  8. *
  9. * Copyright (C) 2004-2010
  10. * Texas Instruments Incorporated - http://www.ti.com/
  11. *
  12. * Copyright (C) 2011
  13. * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
  14. *
  15. * Author :
  16. * Vaibhav Hiremath <hvaibhav@ti.com>
  17. *
  18. * Original implementation by (mem.c, board.c) :
  19. * Sunil Kumar <sunilsaini05@gmail.com>
  20. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  21. * Manikandan Pillai <mani.pillai@ti.com>
  22. */
  23. #include <common.h>
  24. #include <init.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/mem.h>
  27. #include <asm/arch/sys_proto.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. extern omap3_sysinfo sysinfo;
  30. static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  31. /*
  32. * is_mem_sdr -
  33. * - Return 1 if mem type in use is SDR
  34. */
  35. u32 is_mem_sdr(void)
  36. {
  37. if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
  38. return 1;
  39. return 0;
  40. }
  41. /*
  42. * make_cs1_contiguous -
  43. * - When we have CS1 populated we want to have it mapped after cs0 to allow
  44. * command line mem=xyz use all memory with out discontinuous support
  45. * compiled in. We could do it in the ATAG, but there really is two banks...
  46. */
  47. void make_cs1_contiguous(void)
  48. {
  49. u32 size, a_add_low, a_add_high;
  50. size = get_sdr_cs_size(CS0);
  51. size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
  52. a_add_high = (size & 3) << 8; /* set up low field */
  53. a_add_low = (size & 0x3C) >> 2; /* set up high field */
  54. writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
  55. }
  56. /*
  57. * get_sdr_cs_size -
  58. * - Get size of chip select 0/1
  59. */
  60. u32 get_sdr_cs_size(u32 cs)
  61. {
  62. u32 size;
  63. /* get ram size field */
  64. size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
  65. size &= 0x3FF; /* remove unwanted bits */
  66. size <<= 21; /* multiply by 2 MiB to find size in MB */
  67. return size;
  68. }
  69. /*
  70. * get_sdr_cs_offset -
  71. * - Get offset of cs from cs0 start
  72. */
  73. u32 get_sdr_cs_offset(u32 cs)
  74. {
  75. u32 offset;
  76. if (!cs)
  77. return 0;
  78. offset = readl(&sdrc_base->cs_cfg);
  79. offset = (offset & 15) << 27 | (offset & 0x300) << 17;
  80. return offset;
  81. }
  82. /*
  83. * write_sdrc_timings -
  84. * - Takes CS and associated timings and initalize SDRAM
  85. * - Test CS to make sure it's OK for use
  86. */
  87. static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
  88. struct board_sdrc_timings *timings)
  89. {
  90. /* Setup timings we got from the board. */
  91. writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
  92. writel(timings->ctrla, &sdrc_actim_base->ctrla);
  93. writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
  94. writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
  95. writel(CMD_NOP, &sdrc_base->cs[cs].manual);
  96. writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
  97. writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
  98. writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
  99. writel(timings->mr, &sdrc_base->cs[cs].mr);
  100. /*
  101. * Test ram in this bank
  102. * Disable if bad or not present
  103. */
  104. if (!mem_ok(cs))
  105. writel(0, &sdrc_base->cs[cs].mcfg);
  106. }
  107. /*
  108. * do_sdrc_init -
  109. * - Code called once in C-Stack only context for CS0 and with early being
  110. * true and a possible 2nd time depending on memory configuration from
  111. * stack+global context.
  112. */
  113. void do_sdrc_init(u32 cs, u32 early)
  114. {
  115. struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
  116. struct board_sdrc_timings timings;
  117. sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
  118. sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
  119. /* set some default timings */
  120. timings.sharing = SDRC_SHARING;
  121. /*
  122. * When called in the early context this may be SPL and we will
  123. * need to set all of the timings. This ends up being board
  124. * specific so we call a helper function to take care of this
  125. * for us. Otherwise, to be safe, we need to copy the settings
  126. * from the first bank to the second. We will setup CS0,
  127. * then set cs_cfg to the appropriate value then try and
  128. * setup CS1.
  129. */
  130. #ifdef CONFIG_SPL_BUILD
  131. /* set/modify board-specific timings */
  132. get_board_mem_timings(&timings);
  133. #endif
  134. if (early) {
  135. /* reset sdrc controller */
  136. writel(SOFTRESET, &sdrc_base->sysconfig);
  137. wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
  138. 12000000);
  139. writel(0, &sdrc_base->sysconfig);
  140. /* setup sdrc to ball mux */
  141. writel(timings.sharing, &sdrc_base->sharing);
  142. /* Disable Power Down of CKE because of 1 CKE on combo part */
  143. writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
  144. &sdrc_base->power);
  145. writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
  146. sdelay(0x20000);
  147. #ifdef CONFIG_SPL_BUILD
  148. write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
  149. make_cs1_contiguous();
  150. write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
  151. #endif
  152. }
  153. /*
  154. * If we aren't using SPL we have been loaded by some
  155. * other means which may not have correctly initialized
  156. * both CS0 and CS1 (such as some older versions of x-loader)
  157. * so we may be asked now to setup CS1.
  158. */
  159. if (cs == CS1) {
  160. timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
  161. timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
  162. timings.ctrla = readl(&sdrc_actim_base0->ctrla);
  163. timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
  164. timings.mr = readl(&sdrc_base->cs[CS0].mr);
  165. write_sdrc_timings(cs, sdrc_actim_base1, &timings);
  166. }
  167. }
  168. /*
  169. * dram_init -
  170. * - Sets uboots idea of sdram size
  171. */
  172. int dram_init(void)
  173. {
  174. unsigned int size0 = 0, size1 = 0;
  175. size0 = get_sdr_cs_size(CS0);
  176. /*
  177. * We always need to have cs_cfg point at where the second
  178. * bank would be, if present. Failure to do so can lead to
  179. * strange situations where memory isn't detected and
  180. * configured correctly. CS0 will already have been setup
  181. * at this point.
  182. */
  183. make_cs1_contiguous();
  184. do_sdrc_init(CS1, NOT_EARLY);
  185. size1 = get_sdr_cs_size(CS1);
  186. gd->ram_size = size0 + size1;
  187. return 0;
  188. }
  189. int dram_init_banksize(void)
  190. {
  191. unsigned int size0 = 0, size1 = 0;
  192. size0 = get_sdr_cs_size(CS0);
  193. size1 = get_sdr_cs_size(CS1);
  194. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  195. gd->bd->bi_dram[0].size = size0;
  196. gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
  197. gd->bd->bi_dram[1].size = size1;
  198. return 0;
  199. }
  200. /*
  201. * mem_init -
  202. * - Init the sdrc chip,
  203. * - Selects CS0 and CS1,
  204. */
  205. void mem_init(void)
  206. {
  207. /* only init up first bank here */
  208. do_sdrc_init(CS0, EARLY_INIT);
  209. }