board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Common board functions for OMAP3 based boards.
  5. *
  6. * (C) Copyright 2004-2008
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Sunil Kumar <sunilsaini05@gmail.com>
  11. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  12. *
  13. * Derived from Beagle Board and 3430 SDP code by
  14. * Richard Woodruff <r-woodruff2@ti.com>
  15. * Syed Mohammed Khasim <khasim@ti.com>
  16. *
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <init.h>
  21. #include <spl.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/cache.h>
  26. #include <asm/armv7.h>
  27. #include <asm/gpio.h>
  28. #include <asm/omap_common.h>
  29. #include <linux/compiler.h>
  30. /* Declarations */
  31. extern omap3_sysinfo sysinfo;
  32. #ifndef CONFIG_SYS_L2CACHE_OFF
  33. static void omap3_invalidate_l2_cache_secure(void);
  34. #endif
  35. #if CONFIG_IS_ENABLED(DM_GPIO)
  36. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  37. /* Manually initialize GPIO banks when OF_CONTROL doesn't */
  38. static const struct omap_gpio_platdata omap34xx_gpio[] = {
  39. { 0, OMAP34XX_GPIO1_BASE },
  40. { 1, OMAP34XX_GPIO2_BASE },
  41. { 2, OMAP34XX_GPIO3_BASE },
  42. { 3, OMAP34XX_GPIO4_BASE },
  43. { 4, OMAP34XX_GPIO5_BASE },
  44. { 5, OMAP34XX_GPIO6_BASE },
  45. };
  46. U_BOOT_DEVICES(omap34xx_gpios) = {
  47. { "gpio_omap", &omap34xx_gpio[0] },
  48. { "gpio_omap", &omap34xx_gpio[1] },
  49. { "gpio_omap", &omap34xx_gpio[2] },
  50. { "gpio_omap", &omap34xx_gpio[3] },
  51. { "gpio_omap", &omap34xx_gpio[4] },
  52. { "gpio_omap", &omap34xx_gpio[5] },
  53. };
  54. #endif
  55. #else
  56. static const struct gpio_bank gpio_bank_34xx[6] = {
  57. { (void *)OMAP34XX_GPIO1_BASE },
  58. { (void *)OMAP34XX_GPIO2_BASE },
  59. { (void *)OMAP34XX_GPIO3_BASE },
  60. { (void *)OMAP34XX_GPIO4_BASE },
  61. { (void *)OMAP34XX_GPIO5_BASE },
  62. { (void *)OMAP34XX_GPIO6_BASE },
  63. };
  64. const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  65. #endif
  66. /******************************************************************************
  67. * Routine: secure_unlock
  68. * Description: Setup security registers for access
  69. * (GP Device only)
  70. *****************************************************************************/
  71. void secure_unlock_mem(void)
  72. {
  73. struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
  74. struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
  75. struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
  76. struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
  77. struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
  78. /* Protection Module Register Target APE (PM_RT) */
  79. writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
  80. writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
  81. writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
  82. writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
  83. writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
  84. writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
  85. writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
  86. writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
  87. writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
  88. writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
  89. writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
  90. /* IVA Changes */
  91. writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
  92. writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
  93. writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
  94. /* SDRC region 0 public */
  95. writel(UNLOCK_1, &sms_base->rg_att0);
  96. }
  97. /******************************************************************************
  98. * Routine: secureworld_exit()
  99. * Description: If chip is EMU and boot type is external
  100. * configure secure registers and exit secure world
  101. * general use.
  102. *****************************************************************************/
  103. void secureworld_exit(void)
  104. {
  105. unsigned long i;
  106. /* configure non-secure access control register */
  107. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
  108. /* enabling co-processor CP10 and CP11 accesses in NS world */
  109. __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
  110. /*
  111. * allow allocation of locked TLBs and L2 lines in NS world
  112. * allow use of PLE registers in NS world also
  113. */
  114. __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
  115. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
  116. /* Enable ASA in ACR register */
  117. __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
  118. __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
  119. __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
  120. /* Exiting secure world */
  121. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
  122. __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
  123. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
  124. }
  125. /******************************************************************************
  126. * Routine: try_unlock_sram()
  127. * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  128. * general use.
  129. *****************************************************************************/
  130. void try_unlock_memory(void)
  131. {
  132. int mode;
  133. int in_sdram = is_running_in_sdram();
  134. /*
  135. * if GP device unlock device SRAM for general use
  136. * secure code breaks for Secure/Emulation device - HS/E/T
  137. */
  138. mode = get_device_type();
  139. if (mode == GP_DEVICE)
  140. secure_unlock_mem();
  141. /*
  142. * If device is EMU and boot is XIP external booting
  143. * Unlock firewalls and disable L2 and put chip
  144. * out of secure world
  145. *
  146. * Assuming memories are unlocked by the demon who put us in SDRAM
  147. */
  148. if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
  149. && (!in_sdram)) {
  150. secure_unlock_mem();
  151. secureworld_exit();
  152. }
  153. return;
  154. }
  155. void early_system_init(void)
  156. {
  157. hw_data_init();
  158. }
  159. /******************************************************************************
  160. * Routine: s_init
  161. * Description: Does early system init of muxing and clocks.
  162. * - Called path is with SRAM stack.
  163. *****************************************************************************/
  164. void s_init(void)
  165. {
  166. watchdog_init();
  167. early_system_init();
  168. try_unlock_memory();
  169. #ifndef CONFIG_SYS_L2CACHE_OFF
  170. /* Invalidate L2-cache from secure mode */
  171. omap3_invalidate_l2_cache_secure();
  172. #endif
  173. set_muxconf_regs();
  174. sdelay(100);
  175. prcm_init();
  176. per_clocks_enable();
  177. #ifdef CONFIG_USB_EHCI_OMAP
  178. ehci_clocks_enable();
  179. #endif
  180. }
  181. #ifdef CONFIG_SPL_BUILD
  182. void board_init_f(ulong dummy)
  183. {
  184. early_system_init();
  185. mem_init();
  186. /*
  187. * Save the boot parameters passed from romcode.
  188. * We cannot delay the saving further than this,
  189. * to prevent overwrites.
  190. */
  191. save_omap_boot_params();
  192. }
  193. #endif
  194. /*
  195. * Routine: misc_init_r
  196. * Description: A basic misc_init_r that just displays the die ID
  197. */
  198. int __weak misc_init_r(void)
  199. {
  200. omap_die_id_display();
  201. return 0;
  202. }
  203. /******************************************************************************
  204. * Routine: wait_for_command_complete
  205. * Description: Wait for posting to finish on watchdog
  206. *****************************************************************************/
  207. static void wait_for_command_complete(struct watchdog *wd_base)
  208. {
  209. int pending = 1;
  210. do {
  211. pending = readl(&wd_base->wwps);
  212. } while (pending);
  213. }
  214. /******************************************************************************
  215. * Routine: watchdog_init
  216. * Description: Shut down watch dogs
  217. *****************************************************************************/
  218. void watchdog_init(void)
  219. {
  220. struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
  221. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  222. /*
  223. * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
  224. * either taken care of by ROM (HS/EMU) or not accessible (GP).
  225. * We need to take care of WD2-MPU or take a PRCM reset. WD3
  226. * should not be running and does not generate a PRCM reset.
  227. */
  228. setbits_le32(&prcm_base->fclken_wkup, 0x20);
  229. setbits_le32(&prcm_base->iclken_wkup, 0x20);
  230. wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
  231. writel(WD_UNLOCK1, &wd2_base->wspr);
  232. wait_for_command_complete(wd2_base);
  233. writel(WD_UNLOCK2, &wd2_base->wspr);
  234. }
  235. /******************************************************************************
  236. * Dummy function to handle errors for EABI incompatibility
  237. *****************************************************************************/
  238. void abort(void)
  239. {
  240. }
  241. #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
  242. /******************************************************************************
  243. * OMAP3 specific command to switch between NAND HW and SW ecc
  244. *****************************************************************************/
  245. static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  246. {
  247. int hw, strength = 1;
  248. if (argc < 2 || argc > 3)
  249. goto usage;
  250. if (strncmp(argv[1], "hw", 2) == 0) {
  251. hw = 1;
  252. if (argc == 3) {
  253. if (strncmp(argv[2], "bch8", 4) == 0)
  254. strength = 8;
  255. else if (strncmp(argv[2], "bch16", 5) == 0)
  256. strength = 16;
  257. else if (strncmp(argv[2], "hamming", 7) != 0)
  258. goto usage;
  259. }
  260. } else if (strncmp(argv[1], "sw", 2) == 0) {
  261. hw = 0;
  262. if (argc == 3) {
  263. if (strncmp(argv[2], "bch8", 4) == 0)
  264. strength = 8;
  265. else if (strncmp(argv[2], "hamming", 7) != 0)
  266. goto usage;
  267. }
  268. } else {
  269. goto usage;
  270. }
  271. return -omap_nand_switch_ecc(hw, strength);
  272. usage:
  273. printf ("Usage: nandecc %s\n", cmdtp->usage);
  274. return 1;
  275. }
  276. U_BOOT_CMD(
  277. nandecc, 3, 1, do_switch_ecc,
  278. "switch OMAP3 NAND ECC calculation algorithm",
  279. "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
  280. " and 8-bit/16-bit BCH\n"
  281. " ecc calculation (second parameter may"
  282. " be omitted).\n"
  283. "nandecc sw - Switch to NAND software ecc algorithm."
  284. );
  285. #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
  286. #ifdef CONFIG_DISPLAY_BOARDINFO
  287. /**
  288. * Print board information
  289. */
  290. int checkboard (void)
  291. {
  292. char *mem_s ;
  293. if (is_mem_sdr())
  294. mem_s = "mSDR";
  295. else
  296. mem_s = "LPDDR";
  297. printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
  298. sysinfo.nand_string);
  299. return 0;
  300. }
  301. #endif /* CONFIG_DISPLAY_BOARDINFO */
  302. static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
  303. {
  304. u32 i, num_params = *parameters;
  305. u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
  306. /*
  307. * copy the parameters to an un-cached area to avoid coherency
  308. * issues
  309. */
  310. for (i = 0; i < num_params; i++) {
  311. __raw_writel(*parameters, sram_scratch_space);
  312. parameters++;
  313. sram_scratch_space++;
  314. }
  315. /* Now make the PPA call */
  316. do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
  317. }
  318. void __weak omap3_set_aux_cr_secure(u32 acr)
  319. {
  320. struct emu_hal_params emu_romcode_params;
  321. emu_romcode_params.num_params = 1;
  322. emu_romcode_params.param1 = acr;
  323. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
  324. (u32 *)&emu_romcode_params);
  325. }
  326. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  327. u32 cpu_rev_comb, u32 cpu_variant,
  328. u32 cpu_rev)
  329. {
  330. if (get_device_type() == GP_DEVICE)
  331. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
  332. /* L2 Cache Auxiliary Control Register is not banked */
  333. }
  334. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  335. u32 cpu_variant, u32 cpu_rev)
  336. {
  337. /* Write ACR - affects secure banked bits */
  338. if (get_device_type() == GP_DEVICE)
  339. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
  340. else
  341. omap3_set_aux_cr_secure(acr);
  342. /* Write ACR - affects non-secure banked bits - some erratas need it */
  343. asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
  344. }
  345. #ifndef CONFIG_SYS_L2CACHE_OFF
  346. static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
  347. {
  348. u32 acr;
  349. /* Read ACR */
  350. asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  351. acr &= ~clear_bits;
  352. acr |= set_bits;
  353. v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
  354. }
  355. /* Invalidate the entire L2 cache from secure mode */
  356. static void omap3_invalidate_l2_cache_secure(void)
  357. {
  358. if (get_device_type() == GP_DEVICE) {
  359. omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
  360. } else {
  361. struct emu_hal_params emu_romcode_params;
  362. emu_romcode_params.num_params = 1;
  363. emu_romcode_params.param1 = 0;
  364. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
  365. (u32 *)&emu_romcode_params);
  366. }
  367. }
  368. void v7_outer_cache_enable(void)
  369. {
  370. /*
  371. * Set L2EN
  372. * On some revisions L2EN bit is banked on some revisions it's not
  373. * No harm in setting both banked bits(in fact this is required
  374. * by an erratum)
  375. */
  376. omap3_update_aux_cr(0x2, 0);
  377. }
  378. void omap3_outer_cache_disable(void)
  379. {
  380. /*
  381. * Clear L2EN
  382. * On some revisions L2EN bit is banked on some revisions it's not
  383. * No harm in clearing both banked bits(in fact this is required
  384. * by an erratum)
  385. */
  386. omap3_update_aux_cr(0, 0x2);
  387. }
  388. #endif /* !CONFIG_SYS_L2CACHE_OFF */