chilisom.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  4. * Copyright (C) 2017, Grinn - http://grinn-global.com/
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/clk_synthesizer.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/ddr_defs.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/omap.h>
  14. #include <asm/arch/mem.h>
  15. #include <asm/arch/mux.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/emif.h>
  18. #include <asm/io.h>
  19. #include <errno.h>
  20. #include <i2c.h>
  21. #include <power/tps65217.h>
  22. #include <spl.h>
  23. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  24. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  25. static struct module_pin_mux i2c0_pin_mux[] = {
  26. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  27. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  28. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  29. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  30. {-1},
  31. };
  32. static struct module_pin_mux nand_pin_mux[] = {
  33. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  34. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  35. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  36. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  37. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  38. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  39. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  40. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  41. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  42. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  43. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  44. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  45. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  46. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  47. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  48. {-1},
  49. };
  50. static void enable_i2c0_pin_mux(void)
  51. {
  52. configure_module_pin_mux(i2c0_pin_mux);
  53. }
  54. void chilisom_enable_pin_mux(void)
  55. {
  56. /* chilisom pin mux */
  57. configure_module_pin_mux(nand_pin_mux);
  58. }
  59. static const struct ddr_data ddr3_chilisom_data = {
  60. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  61. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  62. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  63. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  64. };
  65. static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = {
  66. .cmd0csratio = MT41K256M16HA125E_RATIO,
  67. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  68. .cmd1csratio = MT41K256M16HA125E_RATIO,
  69. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  70. .cmd2csratio = MT41K256M16HA125E_RATIO,
  71. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  72. };
  73. static struct emif_regs ddr3_chilisom_emif_reg_data = {
  74. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  75. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  76. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  77. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  78. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  79. .ocp_config = 0x00141414,
  80. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  81. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  82. };
  83. void chilisom_spl_board_init(void)
  84. {
  85. int mpu_vdd;
  86. int usb_cur_lim;
  87. enable_i2c0_pin_mux();
  88. /* Get the frequency */
  89. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  90. if (i2c_probe(TPS65217_CHIP_PM))
  91. return;
  92. /*
  93. * Increase USB current limit to 1300mA or 1800mA and set
  94. * the MPU voltage controller as needed.
  95. */
  96. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  97. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  98. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  99. } else {
  100. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  101. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  102. }
  103. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  104. TPS65217_POWER_PATH,
  105. usb_cur_lim,
  106. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  107. puts("tps65217_reg_write failure\n");
  108. /* Set DCDC3 (CORE) voltage to 1.125V */
  109. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  110. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  111. puts("tps65217_voltage_update failure\n");
  112. return;
  113. }
  114. /* Set CORE Frequencies to OPP100 */
  115. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  116. /* Set DCDC2 (MPU) voltage */
  117. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  118. puts("tps65217_voltage_update failure\n");
  119. return;
  120. }
  121. /* Set LDO3 to 1.8V and LDO4 to 3.3V */
  122. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  123. TPS65217_DEFLS1,
  124. TPS65217_LDO_VOLTAGE_OUT_1_8,
  125. TPS65217_LDO_MASK))
  126. puts("tps65217_reg_write failure\n");
  127. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  128. TPS65217_DEFLS2,
  129. TPS65217_LDO_VOLTAGE_OUT_3_3,
  130. TPS65217_LDO_MASK))
  131. puts("tps65217_reg_write failure\n");
  132. /* Set MPU Frequency to what we detected now that voltages are set */
  133. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  134. }
  135. #define OSC (V_OSCK/1000000)
  136. const struct dpll_params dpll_ddr_chilisom = {
  137. 400, OSC-1, 1, -1, -1, -1, -1};
  138. const struct dpll_params *get_dpll_ddr_params(void)
  139. {
  140. return &dpll_ddr_chilisom;
  141. }
  142. const struct ctrl_ioregs ioregs_chilisom = {
  143. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  144. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  145. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  146. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  147. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  148. };
  149. void sdram_init(void)
  150. {
  151. config_ddr(400, &ioregs_chilisom,
  152. &ddr3_chilisom_data,
  153. &ddr3_chilisom_cmd_ctrl_data,
  154. &ddr3_chilisom_emif_reg_data, 0);
  155. }
  156. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */