cpu.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. * Copyright (C) 2020 Marek Behun <marek.behun@nic.cz>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <linux/libfdt.h>
  12. #include <asm/io.h>
  13. #include <asm/system.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/armv8/mmu.h>
  17. #include <sort.h>
  18. /* Armada 3700 */
  19. #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
  20. #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
  21. #define MVEBU_XTAL_MODE_MASK BIT(9)
  22. #define MVEBU_XTAL_MODE_OFFS 9
  23. #define MVEBU_XTAL_CLOCK_25MHZ 0x0
  24. #define MVEBU_XTAL_CLOCK_40MHZ 0x1
  25. #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
  26. #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
  27. /* Armada 3700 CPU Address Decoder registers */
  28. #define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
  29. #define MVEBU_CPU_DEC_WIN_CTRL(w) \
  30. (MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
  31. #define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
  32. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
  33. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
  34. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
  35. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
  36. #define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
  37. #define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
  38. #define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
  39. #define MVEBU_CPU_DEC_WIN_GRANULARITY 16
  40. #define MVEBU_CPU_DEC_WINS 5
  41. #define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
  42. #define A3700_PTE_BLOCK_NORMAL \
  43. (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
  44. #define A3700_PTE_BLOCK_DEVICE \
  45. (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
  46. #define PCIE_PATH "/soc/pcie@d0070000"
  47. DECLARE_GLOBAL_DATA_PTR;
  48. static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
  49. {
  50. /*
  51. * SRAM, MMIO regions
  52. * Don't remove this, a3700_build_mem_map needs it.
  53. */
  54. .phys = SOC_REGS_PHY_BASE,
  55. .virt = SOC_REGS_PHY_BASE,
  56. .size = 0x02000000UL, /* 32MiB internal registers */
  57. .attrs = A3700_PTE_BLOCK_DEVICE
  58. },
  59. };
  60. struct mm_region *mem_map = mvebu_mem_map;
  61. static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
  62. {
  63. u32 reg;
  64. reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
  65. if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
  66. return -1;
  67. if (tgt) {
  68. reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
  69. reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
  70. *tgt = reg;
  71. }
  72. if (base) {
  73. reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
  74. *base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
  75. }
  76. if (size) {
  77. /*
  78. * Window size is encoded as the number of 1s from LSB to MSB,
  79. * followed by 0s. The number of 1s specifies the size in 64 KiB
  80. * granularity.
  81. */
  82. reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
  83. *size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
  84. }
  85. return 0;
  86. }
  87. /*
  88. * Builds mem_map according to CPU Address Decoder settings, which were set by
  89. * the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
  90. */
  91. static void build_mem_map(void)
  92. {
  93. int win, region;
  94. region = 1;
  95. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  96. u32 base, tgt, size;
  97. u64 attrs;
  98. /* skip disabled windows */
  99. if (get_cpu_dec_win(win, &tgt, &base, &size))
  100. continue;
  101. if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  102. attrs = A3700_PTE_BLOCK_NORMAL;
  103. else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
  104. attrs = A3700_PTE_BLOCK_DEVICE;
  105. else
  106. /* skip windows with other targets */
  107. continue;
  108. mvebu_mem_map[region].phys = base;
  109. mvebu_mem_map[region].virt = base;
  110. mvebu_mem_map[region].size = size;
  111. mvebu_mem_map[region].attrs = attrs;
  112. ++region;
  113. }
  114. /* add list terminator */
  115. mvebu_mem_map[region].size = 0;
  116. mvebu_mem_map[region].attrs = 0;
  117. }
  118. void enable_caches(void)
  119. {
  120. build_mem_map();
  121. icache_enable();
  122. dcache_enable();
  123. }
  124. int a3700_dram_init(void)
  125. {
  126. int win;
  127. gd->ram_size = 0;
  128. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  129. u32 base, tgt, size;
  130. /* skip disabled windows */
  131. if (get_cpu_dec_win(win, &tgt, &base, &size))
  132. continue;
  133. /* skip non-DRAM windows */
  134. if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  135. continue;
  136. /*
  137. * It is possible that one image was built for boards with
  138. * different RAM sizes, for example 512 MiB and 1 GiB.
  139. * We therefore try to determine the actual RAM size in the
  140. * window with get_ram_size.
  141. */
  142. gd->ram_size += get_ram_size((void *)(size_t)base, size);
  143. }
  144. return 0;
  145. }
  146. struct a3700_dram_window {
  147. size_t base, size;
  148. };
  149. static int dram_win_cmp(const void *a, const void *b)
  150. {
  151. size_t ab, bb;
  152. ab = ((const struct a3700_dram_window *)a)->base;
  153. bb = ((const struct a3700_dram_window *)b)->base;
  154. if (ab < bb)
  155. return -1;
  156. else if (ab > bb)
  157. return 1;
  158. else
  159. return 0;
  160. }
  161. int a3700_dram_init_banksize(void)
  162. {
  163. struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
  164. int bank, win, ndram_wins;
  165. u32 last_end;
  166. size_t size;
  167. ndram_wins = 0;
  168. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  169. u32 base, tgt, size;
  170. /* skip disabled windows */
  171. if (get_cpu_dec_win(win, &tgt, &base, &size))
  172. continue;
  173. /* skip non-DRAM windows */
  174. if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  175. continue;
  176. dram_wins[win].base = base;
  177. dram_wins[win].size = size;
  178. ++ndram_wins;
  179. }
  180. qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
  181. bank = 0;
  182. last_end = -1;
  183. for (win = 0; win < ndram_wins; ++win) {
  184. /* again determining actual RAM size as in a3700_dram_init */
  185. size = get_ram_size((void *)dram_wins[win].base,
  186. dram_wins[win].size);
  187. /*
  188. * Check if previous window ends as the current starts. If yes,
  189. * merge these windows into one "bank". This is possible by this
  190. * simple check thanks to mem_map regions being qsorted in
  191. * build_mem_map.
  192. */
  193. if (last_end == dram_wins[win].base) {
  194. gd->bd->bi_dram[bank - 1].size += size;
  195. last_end += size;
  196. } else {
  197. if (bank == CONFIG_NR_DRAM_BANKS) {
  198. printf("Need more CONFIG_NR_DRAM_BANKS\n");
  199. return -ENOBUFS;
  200. }
  201. gd->bd->bi_dram[bank].start = dram_wins[win].base;
  202. gd->bd->bi_dram[bank].size = size;
  203. last_end = dram_wins[win].base + size;
  204. ++bank;
  205. }
  206. }
  207. /*
  208. * If there is more place for DRAM BANKS definitions than needed, fill
  209. * the rest with zeros.
  210. */
  211. for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
  212. gd->bd->bi_dram[bank].start = 0;
  213. gd->bd->bi_dram[bank].size = 0;
  214. }
  215. return 0;
  216. }
  217. static u32 find_pcie_window_base(void)
  218. {
  219. int win;
  220. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  221. u32 base, tgt;
  222. /* skip disabled windows */
  223. if (get_cpu_dec_win(win, &tgt, &base, NULL))
  224. continue;
  225. if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
  226. return base;
  227. }
  228. return -1;
  229. }
  230. int a3700_fdt_fix_pcie_regions(void *blob)
  231. {
  232. u32 new_ranges[14], base;
  233. const u32 *ranges;
  234. int node, len;
  235. node = fdt_path_offset(blob, PCIE_PATH);
  236. if (node < 0)
  237. return node;
  238. ranges = fdt_getprop(blob, node, "ranges", &len);
  239. if (!ranges)
  240. return -ENOENT;
  241. if (len != sizeof(new_ranges))
  242. return -EINVAL;
  243. memcpy(new_ranges, ranges, len);
  244. base = find_pcie_window_base();
  245. if (base == -1)
  246. return -ENOENT;
  247. new_ranges[2] = cpu_to_fdt32(base);
  248. new_ranges[4] = new_ranges[2];
  249. new_ranges[9] = cpu_to_fdt32(base + 0x1000000);
  250. new_ranges[11] = new_ranges[9];
  251. return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
  252. }
  253. void reset_cpu(ulong ignored)
  254. {
  255. /*
  256. * Write magic number of 0x1d1e to North Bridge Warm Reset register
  257. * to trigger warm reset
  258. */
  259. writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
  260. }
  261. /*
  262. * get_ref_clk
  263. *
  264. * return: reference clock in MHz (25 or 40)
  265. */
  266. u32 get_ref_clk(void)
  267. {
  268. u32 regval;
  269. regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
  270. MVEBU_XTAL_MODE_OFFS;
  271. if (regval == MVEBU_XTAL_CLOCK_25MHZ)
  272. return 25;
  273. else
  274. return 40;
  275. }