init.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <ram.h>
  12. #include <asm/arch/misc.h>
  13. #include <asm/sections.h>
  14. #include <dm/uclass.h>
  15. #include <linux/io.h>
  16. #include <dt-bindings/clock/mt7629-clk.h>
  17. #define L2_CFG_BASE 0x10200000
  18. #define L2_CFG_SIZE 0x1000
  19. #define L2_SHARE_CFG_MP0 0x7f0
  20. #define L2_SHARE_MODE_OFF BIT(8)
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int mtk_pll_early_init(void)
  23. {
  24. unsigned long pll_rates[] = {
  25. [CLK_APMIXED_ARMPLL] = 1250000000,
  26. [CLK_APMIXED_MAINPLL] = 1120000000,
  27. [CLK_APMIXED_UNIV2PLL] = 1200000000,
  28. [CLK_APMIXED_ETH1PLL] = 500000000,
  29. [CLK_APMIXED_ETH2PLL] = 700000000,
  30. [CLK_APMIXED_SGMIPLL] = 650000000,
  31. };
  32. struct udevice *dev;
  33. int ret, i;
  34. ret = uclass_get_device_by_driver(UCLASS_CLK,
  35. DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  36. if (ret)
  37. return ret;
  38. /* configure default rate then enable apmixedsys */
  39. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  40. struct clk clk = { .id = i, .dev = dev };
  41. ret = clk_set_rate(&clk, pll_rates[i]);
  42. if (ret)
  43. return ret;
  44. ret = clk_enable(&clk);
  45. if (ret)
  46. return ret;
  47. }
  48. /* setup mcu bus */
  49. ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  50. DM_GET_DRIVER(mtk_mcucfg), &dev);
  51. if (ret)
  52. return ret;
  53. return 0;
  54. }
  55. int mtk_soc_early_init(void)
  56. {
  57. struct udevice *dev;
  58. int ret;
  59. /* initialize early clocks */
  60. ret = mtk_pll_early_init();
  61. if (ret)
  62. return ret;
  63. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  64. if (ret)
  65. return ret;
  66. return 0;
  67. }
  68. int mach_cpu_init(void)
  69. {
  70. void __iomem *base;
  71. base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
  72. /* disable L2C shared mode */
  73. writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
  74. return 0;
  75. }
  76. int dram_init(void)
  77. {
  78. struct ram_info ram;
  79. struct udevice *dev;
  80. int ret;
  81. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  82. if (ret)
  83. return ret;
  84. ret = ram_get_info(dev, &ram);
  85. if (ret)
  86. return ret;
  87. debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
  88. gd->ram_size = ram.size;
  89. return 0;
  90. }
  91. int print_cpuinfo(void)
  92. {
  93. void __iomem *chipid;
  94. u32 hwcode, swver;
  95. chipid = ioremap(VER_BASE, VER_SIZE);
  96. hwcode = readl(chipid + APHW_CODE);
  97. swver = readl(chipid + APSW_VER);
  98. printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
  99. return 0;
  100. }