init.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: Architecture initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <ns16550.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/msmc.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/psc_defs.h>
  18. #define MAX_PCI_PORTS 2
  19. enum pci_mode {
  20. ENDPOINT,
  21. LEGACY_ENDPOINT,
  22. ROOTCOMPLEX,
  23. };
  24. #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
  25. #define DEVCFG_MODE_SHIFT 1
  26. void chip_configuration_unlock(void)
  27. {
  28. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  29. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  30. }
  31. #ifdef CONFIG_SOC_K2L
  32. void osr_init(void)
  33. {
  34. u32 i;
  35. u32 j;
  36. u32 val;
  37. u32 base = KS2_OSR_CFG_BASE;
  38. u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  39. /* Enable the OSR clock domain */
  40. psc_enable_module(KS2_LPSC_OSR);
  41. /* Disable OSR ECC check for all the ram banks */
  42. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  43. val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  44. (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  45. writel(val , base + KS2_OSR_ECC_VEC);
  46. /**
  47. * wait till read is done.
  48. * Print should be added after earlyprintk support is added.
  49. */
  50. for (j = 0; j < 10000; j++) {
  51. val = readl(base + KS2_OSR_ECC_VEC);
  52. if (val & KS2_OSR_ECC_VEC_RD_DONE)
  53. break;
  54. }
  55. ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  56. KS2_OSR_ECC_CTRL_CHK;
  57. writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  58. writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  59. }
  60. /* Reset OSR memory to all zeros */
  61. for (i = 0; i < KS2_OSR_SIZE; i += 4)
  62. writel(0, KS2_OSR_DATA_BASE + i);
  63. /* Enable OSR ECC check for all the ram banks */
  64. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  65. writel(ecc_ctrl[i] |
  66. KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  67. }
  68. #endif
  69. /* Function to set up PCIe mode */
  70. static void config_pcie_mode(int pcie_port, enum pci_mode mode)
  71. {
  72. u32 val = __raw_readl(KS2_DEVCFG);
  73. if (pcie_port >= MAX_PCI_PORTS)
  74. return;
  75. /**
  76. * each pci port has two bits for mode and it starts at
  77. * bit 1. So use port number to get the right bit position.
  78. */
  79. pcie_port <<= 1;
  80. val &= ~(DEVCFG_MODE_MASK << pcie_port);
  81. val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  82. __raw_writel(val, KS2_DEVCFG);
  83. }
  84. static void msmc_k2hkle_common_setup(void)
  85. {
  86. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  87. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
  88. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
  89. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
  90. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
  91. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  92. }
  93. static void msmc_k2hk_setup(void)
  94. {
  95. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  96. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  97. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  98. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
  99. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
  100. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
  101. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
  102. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  103. }
  104. static inline void msmc_k2l_setup(void)
  105. {
  106. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  107. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  108. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  109. msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
  110. }
  111. static inline void msmc_k2e_setup(void)
  112. {
  113. msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
  114. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  115. msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
  116. }
  117. static void msmc_k2g_setup(void)
  118. {
  119. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  120. msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
  121. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
  122. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
  123. msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
  124. msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
  125. msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
  126. msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
  127. msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
  128. msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
  129. msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
  130. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  131. }
  132. int arch_cpu_init(void)
  133. {
  134. chip_configuration_unlock();
  135. icache_enable();
  136. if (cpu_is_k2g()) {
  137. msmc_k2g_setup();
  138. } else {
  139. msmc_k2hkle_common_setup();
  140. if (cpu_is_k2e())
  141. msmc_k2e_setup();
  142. else if (cpu_is_k2l())
  143. msmc_k2l_setup();
  144. else
  145. msmc_k2hk_setup();
  146. }
  147. /* Initialize the PCIe-0 to work as Root Complex */
  148. config_pcie_mode(0, ROOTCOMPLEX);
  149. #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  150. /* Initialize the PCIe-1 to work as Root Complex */
  151. config_pcie_mode(1, ROOTCOMPLEX);
  152. #endif
  153. #ifdef CONFIG_SOC_K2L
  154. osr_init();
  155. #endif
  156. /*
  157. * just initialise the COM2 port so that TI specific
  158. * UART register PWREMU_MGMT is initialized. Linux UART
  159. * driver doesn't handle this.
  160. */
  161. #ifndef CONFIG_DM_SERIAL
  162. NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
  163. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  164. #endif
  165. return 0;
  166. }
  167. void reset_cpu(ulong addr)
  168. {
  169. volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
  170. u32 tmp;
  171. tmp = *rstctrl & KS2_RSTCTRL_MASK;
  172. *rstctrl = tmp | KS2_RSTCTRL_KEY;
  173. *rstctrl &= KS2_RSTCTRL_SWRST;
  174. for (;;)
  175. ;
  176. }
  177. void enable_caches(void)
  178. {
  179. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  180. /* Enable D-cache. I-cache is already enabled in start.S */
  181. dcache_enable();
  182. #endif
  183. }
  184. #if defined(CONFIG_DISPLAY_CPUINFO)
  185. int print_cpuinfo(void)
  186. {
  187. u16 cpu = get_part_number();
  188. u8 rev = cpu_revision();
  189. puts("CPU: ");
  190. switch (cpu) {
  191. case CPU_66AK2Hx:
  192. puts("66AK2Hx SR");
  193. break;
  194. case CPU_66AK2Lx:
  195. puts("66AK2Lx SR");
  196. break;
  197. case CPU_66AK2Ex:
  198. puts("66AK2Ex SR");
  199. break;
  200. case CPU_66AK2Gx:
  201. puts("66AK2Gx");
  202. #ifdef CONFIG_SOC_K2G
  203. {
  204. int speed = get_max_arm_speed(speeds);
  205. if (speed == SPD1000)
  206. puts("-100 ");
  207. else if (speed == SPD600)
  208. puts("-60 ");
  209. else
  210. puts("-xx ");
  211. }
  212. #endif
  213. puts("SR");
  214. break;
  215. default:
  216. puts("Unknown\n");
  217. }
  218. if (rev == 2)
  219. puts("2.0\n");
  220. else if (rev == 1)
  221. puts("1.1\n");
  222. else if (rev == 0)
  223. puts("1.0\n");
  224. else if (rev == 8)
  225. puts("1.0\n");
  226. return 0;
  227. }
  228. #endif