timer.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <div64.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. /* General purpose timers registers */
  17. struct mxc_gpt {
  18. unsigned int control;
  19. unsigned int prescaler;
  20. unsigned int status;
  21. unsigned int nouse[6];
  22. unsigned int counter;
  23. };
  24. static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
  25. /* General purpose timers bitfields */
  26. #define GPTCR_SWR (1 << 15) /* Software reset */
  27. #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
  28. #define GPTCR_FRR (1 << 9) /* Freerun / restart */
  29. #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
  30. #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
  31. #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
  32. #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
  33. #define GPTCR_TEN 1 /* Timer enable */
  34. #define GPTPR_PRESCALER24M_SHIFT 12
  35. #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
  36. static inline int gpt_has_clk_source_osc(void)
  37. {
  38. #if defined(CONFIG_MX6)
  39. if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
  40. is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
  41. is_mx6ull() || is_mx6sll())
  42. return 1;
  43. return 0;
  44. #else
  45. return 0;
  46. #endif
  47. }
  48. static inline ulong gpt_get_clk(void)
  49. {
  50. #ifdef CONFIG_MXC_GPT_HCLK
  51. if (gpt_has_clk_source_osc())
  52. return MXC_HCLK >> 3;
  53. else
  54. return mxc_get_clock(MXC_IPG_PERCLK);
  55. #else
  56. return MXC_CLK32;
  57. #endif
  58. }
  59. int timer_init(void)
  60. {
  61. int i;
  62. /* setup GP Timer 1 */
  63. __raw_writel(GPTCR_SWR, &cur_gpt->control);
  64. /* We have no udelay by now */
  65. __raw_writel(0, &cur_gpt->control);
  66. i = __raw_readl(&cur_gpt->control);
  67. i &= ~GPTCR_CLKSOURCE_MASK;
  68. #ifdef CONFIG_MXC_GPT_HCLK
  69. if (gpt_has_clk_source_osc()) {
  70. i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
  71. /*
  72. * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
  73. * Enable bit and prescaler
  74. */
  75. if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
  76. is_mx6sll()) {
  77. i |= GPTCR_24MEN;
  78. /* Produce 3Mhz clock */
  79. __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
  80. &cur_gpt->prescaler);
  81. }
  82. } else {
  83. i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
  84. }
  85. #else
  86. __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  87. i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
  88. #endif
  89. __raw_writel(i, &cur_gpt->control);
  90. return 0;
  91. }
  92. unsigned long timer_read_counter(void)
  93. {
  94. return __raw_readl(&cur_gpt->counter); /* current tick value */
  95. }
  96. /*
  97. * This function is derived from PowerPC code (timebase clock frequency).
  98. * On ARM it returns the number of timer ticks per second.
  99. */
  100. ulong get_tbclk(void)
  101. {
  102. return gpt_get_clk();
  103. }
  104. /*
  105. * This function is intended for SHORT delays only.
  106. * It will overflow at around 10 seconds @ 400MHz,
  107. * or 20 seconds @ 200MHz.
  108. */
  109. unsigned long usec2ticks(unsigned long _usec)
  110. {
  111. unsigned long long usec = _usec;
  112. usec *= get_tbclk();
  113. usec += 999999;
  114. do_div(usec, 1000000);
  115. return usec;
  116. }