soc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/mach-imx/dma.h>
  12. #include <asm/mach-imx/hab.h>
  13. #include <asm/mach-imx/rdc-sema.h>
  14. #include <asm/arch/imx-rdc.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <dm.h>
  17. #include <env.h>
  18. #include <imx_thermal.h>
  19. #include <fsl_sec.h>
  20. #include <asm/setup.h>
  21. #define IOMUXC_GPR1 0x4
  22. #define BM_IOMUXC_GPR1_IRQ 0x1000
  23. #define GPC_LPCR_A7_BSC 0x0
  24. #define GPC_LPCR_M4 0x8
  25. #define GPC_SLPCR 0x14
  26. #define GPC_PGC_ACK_SEL_A7 0x24
  27. #define GPC_IMR1_CORE0 0x30
  28. #define GPC_IMR1_CORE1 0x40
  29. #define GPC_IMR1_M4 0x50
  30. #define GPC_PGC_CPU_MAPPING 0xec
  31. #define GPC_PGC_C0_PUPSCR 0x804
  32. #define GPC_PGC_SCU_TIMING 0x890
  33. #define GPC_PGC_C1_PUPSCR 0x844
  34. #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
  35. #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
  36. #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
  37. #define BM_SLPCR_EN_DSM 0x80000000
  38. #define BM_SLPCR_RBC_EN 0x40000000
  39. #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
  40. #define BM_SLPCR_VSTBY 0x4
  41. #define BM_SLPCR_SBYOS 0x2
  42. #define BM_SLPCR_BYPASS_PMIC_READY 0x1
  43. #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
  44. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
  45. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
  46. #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
  47. #if defined(CONFIG_IMX_THERMAL)
  48. static const struct imx_thermal_plat imx7_thermal_plat = {
  49. .regs = (void *)ANATOP_BASE_ADDR,
  50. .fuse_bank = 3,
  51. .fuse_word = 3,
  52. };
  53. U_BOOT_DEVICE(imx7_thermal) = {
  54. .name = "imx_thermal",
  55. .platdata = &imx7_thermal_plat,
  56. };
  57. #endif
  58. #if CONFIG_IS_ENABLED(IMX_RDC)
  59. /*
  60. * In current design, if any peripheral was assigned to both A7 and M4,
  61. * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
  62. * low power mode. So M4 sleep will cause some peripherals fail to work
  63. * at A7 core side. At default, all resources are in domain 0 - 3.
  64. *
  65. * There are 26 peripherals impacted by this IC issue:
  66. * SIM2(sim2/emvsim2)
  67. * SIM1(sim1/emvsim1)
  68. * UART1/UART2/UART3/UART4/UART5/UART6/UART7
  69. * SAI1/SAI2/SAI3
  70. * WDOG1/WDOG2/WDOG3/WDOG4
  71. * GPT1/GPT2/GPT3/GPT4
  72. * PWM1/PWM2/PWM3/PWM4
  73. * ENET1/ENET2
  74. * Software Workaround:
  75. * Here we setup some resources to domain 0 where M4 codes will move
  76. * the M4 out of this domain. Then M4 is not able to access them any longer.
  77. * This is a workaround for ic issue. So the peripherals are not shared
  78. * by them. This way requires the uboot implemented the RDC driver and
  79. * set the 26 IPs above to domain 0 only. M4 code will assign resource
  80. * to its own domain, if it want to use the resource.
  81. */
  82. static rdc_peri_cfg_t const resources[] = {
  83. (RDC_PER_SIM1 | RDC_DOMAIN(0)),
  84. (RDC_PER_SIM2 | RDC_DOMAIN(0)),
  85. (RDC_PER_UART1 | RDC_DOMAIN(0)),
  86. (RDC_PER_UART2 | RDC_DOMAIN(0)),
  87. (RDC_PER_UART3 | RDC_DOMAIN(0)),
  88. (RDC_PER_UART4 | RDC_DOMAIN(0)),
  89. (RDC_PER_UART5 | RDC_DOMAIN(0)),
  90. (RDC_PER_UART6 | RDC_DOMAIN(0)),
  91. (RDC_PER_UART7 | RDC_DOMAIN(0)),
  92. (RDC_PER_SAI1 | RDC_DOMAIN(0)),
  93. (RDC_PER_SAI2 | RDC_DOMAIN(0)),
  94. (RDC_PER_SAI3 | RDC_DOMAIN(0)),
  95. (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
  96. (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
  97. (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
  98. (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
  99. (RDC_PER_GPT1 | RDC_DOMAIN(0)),
  100. (RDC_PER_GPT2 | RDC_DOMAIN(0)),
  101. (RDC_PER_GPT3 | RDC_DOMAIN(0)),
  102. (RDC_PER_GPT4 | RDC_DOMAIN(0)),
  103. (RDC_PER_PWM1 | RDC_DOMAIN(0)),
  104. (RDC_PER_PWM2 | RDC_DOMAIN(0)),
  105. (RDC_PER_PWM3 | RDC_DOMAIN(0)),
  106. (RDC_PER_PWM4 | RDC_DOMAIN(0)),
  107. (RDC_PER_ENET1 | RDC_DOMAIN(0)),
  108. (RDC_PER_ENET2 | RDC_DOMAIN(0)),
  109. };
  110. static void isolate_resource(void)
  111. {
  112. imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
  113. }
  114. #endif
  115. #if defined(CONFIG_IMX_HAB)
  116. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  117. .bank = 1,
  118. .word = 3,
  119. };
  120. #endif
  121. static bool is_mx7d(void)
  122. {
  123. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  124. struct fuse_bank *bank = &ocotp->bank[1];
  125. struct fuse_bank1_regs *fuse =
  126. (struct fuse_bank1_regs *)bank->fuse_regs;
  127. int val;
  128. val = readl(&fuse->tester4);
  129. if (val & 1)
  130. return false;
  131. else
  132. return true;
  133. }
  134. u32 get_cpu_rev(void)
  135. {
  136. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  137. ANATOP_BASE_ADDR;
  138. u32 reg = readl(&ccm_anatop->digprog);
  139. u32 type = (reg >> 16) & 0xff;
  140. if (!is_mx7d())
  141. type = MXC_CPU_MX7S;
  142. reg &= 0xff;
  143. return (type << 12) | reg;
  144. }
  145. #ifdef CONFIG_REVISION_TAG
  146. u32 __weak get_board_rev(void)
  147. {
  148. return get_cpu_rev();
  149. }
  150. #endif
  151. static void imx_enet_mdio_fixup(void)
  152. {
  153. struct iomuxc_gpr_base_regs *gpr_regs =
  154. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  155. /*
  156. * The management data input/output (MDIO) requires open-drain,
  157. * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
  158. * this feature. So to TO1.1, need to enable open drain by setting
  159. * bits GPR0[8:7].
  160. */
  161. if (soc_rev() >= CHIP_REV_1_1) {
  162. setbits_le32(&gpr_regs->gpr[0],
  163. IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
  164. }
  165. }
  166. static void init_cpu_basic(void)
  167. {
  168. imx_enet_mdio_fixup();
  169. #ifdef CONFIG_APBH_DMA
  170. /* Start APBH DMA */
  171. mxs_dma_init();
  172. #endif
  173. }
  174. #ifdef CONFIG_IMX_BOOTAUX
  175. /*
  176. * Table of mappings of physical mem regions in both
  177. * Cortex-A7 and Cortex-M4 address spaces.
  178. *
  179. * For additional details check sections 2.1.2 and 2.1.3 in
  180. * i.MX7Dual Applications Processor Reference Manual
  181. *
  182. */
  183. const struct rproc_att hostmap[] = {
  184. /* aux core , host core, size */
  185. { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
  186. { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
  187. { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
  188. { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
  189. { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
  190. { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
  191. { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
  192. { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
  193. { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
  194. { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
  195. { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
  196. { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
  197. { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
  198. { /* sentinel */ }
  199. };
  200. #endif
  201. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  202. /* enable all periherial can be accessed in nosec mode */
  203. static void init_csu(void)
  204. {
  205. int i = 0;
  206. for (i = 0; i < CSU_NUM_REGS; i++)
  207. writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
  208. }
  209. static void imx_gpcv2_init(void)
  210. {
  211. u32 val, i;
  212. /*
  213. * Force IOMUXC irq pending, so that the interrupt to GPC can be
  214. * used to deassert dsm_request signal when the signal gets
  215. * asserted unexpectedly.
  216. */
  217. val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  218. val |= BM_IOMUXC_GPR1_IRQ;
  219. writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  220. /* Initially mask all interrupts */
  221. for (i = 0; i < 4; i++) {
  222. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  223. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
  224. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
  225. }
  226. /* set SCU timing */
  227. writel((0x59 << 10) | 0x5B | (0x2 << 20),
  228. GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
  229. /* only external IRQs to wake up LPM and core 0/1 */
  230. val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  231. val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
  232. writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  233. /* set C0 power up timming per design requirement */
  234. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  235. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  236. val |= (0x1A << 7);
  237. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  238. /* set C1 power up timming per design requirement */
  239. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  240. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  241. val |= (0x1A << 7);
  242. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  243. /* dummy ack for time slot by default */
  244. writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
  245. BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
  246. GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
  247. /* mask M4 DSM trigger */
  248. writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
  249. BM_LPCR_M4_MASK_DSM_TRIGGER,
  250. GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
  251. /* set mega/fast mix in A7 domain */
  252. writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
  253. /* DSM related settings */
  254. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  255. val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
  256. BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
  257. BM_SLPCR_REG_BYPASS_COUNT);
  258. val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
  259. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  260. /*
  261. * disabling RBC need to delay at least 2 cycles of CKIL(32K)
  262. * due to hardware design requirement, which is
  263. * ~61us, here we use 65us for safe
  264. */
  265. udelay(65);
  266. }
  267. int arch_cpu_init(void)
  268. {
  269. init_aips();
  270. init_csu();
  271. /* Disable PDE bit of WMCR register */
  272. imx_wdog_disable_powerdown();
  273. init_cpu_basic();
  274. #if CONFIG_IS_ENABLED(IMX_RDC)
  275. isolate_resource();
  276. #endif
  277. init_snvs();
  278. imx_gpcv2_init();
  279. return 0;
  280. }
  281. #else
  282. int arch_cpu_init(void)
  283. {
  284. init_cpu_basic();
  285. return 0;
  286. }
  287. #endif
  288. #ifdef CONFIG_ARCH_MISC_INIT
  289. int arch_misc_init(void)
  290. {
  291. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  292. if (is_mx7d())
  293. env_set("soc", "imx7d");
  294. else
  295. env_set("soc", "imx7s");
  296. #endif
  297. #ifdef CONFIG_FSL_CAAM
  298. sec_init();
  299. #endif
  300. return 0;
  301. }
  302. #endif
  303. #ifdef CONFIG_SERIAL_TAG
  304. /*
  305. * OCOTP_TESTER
  306. * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
  307. * OCOTP_TESTER describes a unique ID based on silicon wafer
  308. * and die X/Y position
  309. *
  310. * OCOTOP_TESTER offset 0x410
  311. * 31:0 fuse 0
  312. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  313. *
  314. * OCOTP_TESTER1 offset 0x420
  315. * 31:24 fuse 1
  316. * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  317. * 23:16 fuse 1
  318. * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  319. * 15:11 fuse 1
  320. * The wafer number of the wafer on which the device was fabricated/SJC
  321. * CHALLENGE/ Unique ID
  322. * 10:0 fuse 1
  323. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  324. */
  325. void get_board_serial(struct tag_serialnr *serialnr)
  326. {
  327. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  328. struct fuse_bank *bank = &ocotp->bank[0];
  329. struct fuse_bank0_regs *fuse =
  330. (struct fuse_bank0_regs *)bank->fuse_regs;
  331. serialnr->low = fuse->tester0;
  332. serialnr->high = fuse->tester1;
  333. }
  334. #endif
  335. void set_wdog_reset(struct wdog_regs *wdog)
  336. {
  337. u32 reg = readw(&wdog->wcr);
  338. /*
  339. * Output WDOG_B signal to reset external pmic or POR_B decided by
  340. * the board desgin. Without external reset, the peripherals/DDR/
  341. * PMIC are not reset, that may cause system working abnormal.
  342. */
  343. reg = readw(&wdog->wcr);
  344. reg |= 1 << 3;
  345. /*
  346. * WDZST bit is write-once only bit. Align this bit in kernel,
  347. * otherwise kernel code will have no chance to set this bit.
  348. */
  349. reg |= 1 << 0;
  350. writew(reg, &wdog->wcr);
  351. }
  352. void s_init(void)
  353. {
  354. /* clock configuration. */
  355. clock_init();
  356. return;
  357. }
  358. void reset_misc(void)
  359. {
  360. #ifndef CONFIG_SPL_BUILD
  361. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  362. lcdif_power_down();
  363. #endif
  364. #endif
  365. }