soc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/mach-imx/hab.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/syscounter.h>
  17. #include <asm/armv8/mmu.h>
  18. #include <dm/uclass.h>
  19. #include <errno.h>
  20. #include <fdt_support.h>
  21. #include <fsl_wdog.h>
  22. #include <imx_sip.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #if defined(CONFIG_IMX_HAB)
  25. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  26. .bank = 1,
  27. .word = 3,
  28. };
  29. #endif
  30. int timer_init(void)
  31. {
  32. #ifdef CONFIG_SPL_BUILD
  33. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  34. unsigned long freq = readl(&sctr->cntfid0);
  35. /* Update with accurate clock frequency */
  36. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  37. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  38. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  39. #endif
  40. gd->arch.tbl = 0;
  41. gd->arch.tbu = 0;
  42. return 0;
  43. }
  44. void enable_tzc380(void)
  45. {
  46. struct iomuxc_gpr_base_regs *gpr =
  47. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  48. /* Enable TZASC and lock setting */
  49. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  50. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  51. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  52. setbits_le32(&gpr->gpr[10], BIT(1));
  53. /*
  54. * set Region 0 attribute to allow secure and non-secure
  55. * read/write permission. Found some masters like usb dwc3
  56. * controllers can't work with secure memory.
  57. */
  58. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  59. }
  60. void set_wdog_reset(struct wdog_regs *wdog)
  61. {
  62. /*
  63. * Output WDOG_B signal to reset external pmic or POR_B decided by
  64. * the board design. Without external reset, the peripherals/DDR/
  65. * PMIC are not reset, that may cause system working abnormal.
  66. * WDZST bit is write-once only bit. Align this bit in kernel,
  67. * otherwise kernel code will have no chance to set this bit.
  68. */
  69. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  70. }
  71. static struct mm_region imx8m_mem_map[] = {
  72. {
  73. /* ROM */
  74. .virt = 0x0UL,
  75. .phys = 0x0UL,
  76. .size = 0x100000UL,
  77. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  78. PTE_BLOCK_OUTER_SHARE
  79. }, {
  80. /* CAAM */
  81. .virt = 0x100000UL,
  82. .phys = 0x100000UL,
  83. .size = 0x8000UL,
  84. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  85. PTE_BLOCK_NON_SHARE |
  86. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  87. }, {
  88. /* TCM */
  89. .virt = 0x7C0000UL,
  90. .phys = 0x7C0000UL,
  91. .size = 0x80000UL,
  92. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  93. PTE_BLOCK_NON_SHARE |
  94. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  95. }, {
  96. /* OCRAM */
  97. .virt = 0x900000UL,
  98. .phys = 0x900000UL,
  99. .size = 0x200000UL,
  100. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  101. PTE_BLOCK_OUTER_SHARE
  102. }, {
  103. /* AIPS */
  104. .virt = 0xB00000UL,
  105. .phys = 0xB00000UL,
  106. .size = 0x3f500000UL,
  107. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  108. PTE_BLOCK_NON_SHARE |
  109. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  110. }, {
  111. /* DRAM1 */
  112. .virt = 0x40000000UL,
  113. .phys = 0x40000000UL,
  114. .size = PHYS_SDRAM_SIZE,
  115. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  116. PTE_BLOCK_OUTER_SHARE
  117. #ifdef PHYS_SDRAM_2_SIZE
  118. }, {
  119. /* DRAM2 */
  120. .virt = 0x100000000UL,
  121. .phys = 0x100000000UL,
  122. .size = PHYS_SDRAM_2_SIZE,
  123. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  124. PTE_BLOCK_OUTER_SHARE
  125. #endif
  126. }, {
  127. /* List terminator */
  128. 0,
  129. }
  130. };
  131. struct mm_region *mem_map = imx8m_mem_map;
  132. void enable_caches(void)
  133. {
  134. /*
  135. * If OPTEE runs, remove OPTEE memory from MMU table to
  136. * avoid speculative prefetch. OPTEE runs at the top of
  137. * the first memory bank
  138. */
  139. if (rom_pointer[1])
  140. imx8m_mem_map[5].size -= rom_pointer[1];
  141. icache_enable();
  142. dcache_enable();
  143. }
  144. static u32 get_cpu_variant_type(u32 type)
  145. {
  146. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  147. struct fuse_bank *bank = &ocotp->bank[1];
  148. struct fuse_bank1_regs *fuse =
  149. (struct fuse_bank1_regs *)bank->fuse_regs;
  150. u32 value = readl(&fuse->tester4);
  151. if (type == MXC_CPU_IMX8MQ) {
  152. if ((value & 0x3) == 0x2)
  153. return MXC_CPU_IMX8MD;
  154. else if (value & 0x200000)
  155. return MXC_CPU_IMX8MQL;
  156. } else if (type == MXC_CPU_IMX8MM) {
  157. switch (value & 0x3) {
  158. case 2:
  159. if (value & 0x1c0000)
  160. return MXC_CPU_IMX8MMDL;
  161. else
  162. return MXC_CPU_IMX8MMD;
  163. case 3:
  164. if (value & 0x1c0000)
  165. return MXC_CPU_IMX8MMSL;
  166. else
  167. return MXC_CPU_IMX8MMS;
  168. default:
  169. if (value & 0x1c0000)
  170. return MXC_CPU_IMX8MML;
  171. break;
  172. }
  173. } else if (type == MXC_CPU_IMX8MN) {
  174. switch (value & 0x3) {
  175. case 2:
  176. if (value & 0x1000000)
  177. return MXC_CPU_IMX8MNDL;
  178. else
  179. return MXC_CPU_IMX8MND;
  180. case 3:
  181. if (value & 0x1000000)
  182. return MXC_CPU_IMX8MNSL;
  183. else
  184. return MXC_CPU_IMX8MNS;
  185. default:
  186. if (value & 0x1000000)
  187. return MXC_CPU_IMX8MNL;
  188. break;
  189. }
  190. }
  191. return type;
  192. }
  193. u32 get_cpu_rev(void)
  194. {
  195. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  196. u32 reg = readl(&ana_pll->digprog);
  197. u32 type = (reg >> 16) & 0xff;
  198. u32 major_low = (reg >> 8) & 0xff;
  199. u32 rom_version;
  200. reg &= 0xff;
  201. /* iMX8MP */
  202. if (major_low == 0x43) {
  203. return (MXC_CPU_IMX8MP << 12) | reg;
  204. } else if (major_low == 0x42) {
  205. /* iMX8MN */
  206. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  207. } else if (major_low == 0x41) {
  208. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  209. } else {
  210. if (reg == CHIP_REV_1_0) {
  211. /*
  212. * For B0 chip, the DIGPROG is not updated,
  213. * it is still TO1.0. we have to check ROM
  214. * version or OCOTP_READ_FUSE_DATA.
  215. * 0xff0055aa is magic number for B1.
  216. */
  217. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  218. reg = CHIP_REV_2_1;
  219. } else {
  220. rom_version =
  221. readl((void __iomem *)ROM_VERSION_A0);
  222. if (rom_version != CHIP_REV_1_0) {
  223. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  224. rom_version &= 0xff;
  225. if (rom_version == CHIP_REV_2_0)
  226. reg = CHIP_REV_2_0;
  227. }
  228. }
  229. }
  230. type = get_cpu_variant_type(type);
  231. }
  232. return (type << 12) | reg;
  233. }
  234. static void imx_set_wdog_powerdown(bool enable)
  235. {
  236. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  237. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  238. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  239. /* Write to the PDE (Power Down Enable) bit */
  240. writew(enable, &wdog1->wmcr);
  241. writew(enable, &wdog2->wmcr);
  242. writew(enable, &wdog3->wmcr);
  243. }
  244. int arch_cpu_init_dm(void)
  245. {
  246. struct udevice *dev;
  247. int ret;
  248. if (CONFIG_IS_ENABLED(CLK)) {
  249. ret = uclass_get_device_by_name(UCLASS_CLK,
  250. "clock-controller@30380000",
  251. &dev);
  252. if (ret < 0) {
  253. printf("Failed to find clock node. Check device tree\n");
  254. return ret;
  255. }
  256. }
  257. return 0;
  258. }
  259. int arch_cpu_init(void)
  260. {
  261. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  262. /*
  263. * ROM might disable clock for SCTR,
  264. * enable the clock before timer_init.
  265. */
  266. if (IS_ENABLED(CONFIG_SPL_BUILD))
  267. clock_enable(CCGR_SCTR, 1);
  268. /*
  269. * Init timer at very early state, because sscg pll setting
  270. * will use it
  271. */
  272. timer_init();
  273. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  274. clock_init();
  275. imx_set_wdog_powerdown(false);
  276. }
  277. if (is_imx8mq()) {
  278. clock_enable(CCGR_OCOTP, 1);
  279. if (readl(&ocotp->ctrl) & 0x200)
  280. writel(0x200, &ocotp->ctrl_clr);
  281. }
  282. return 0;
  283. }
  284. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  285. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  286. enum boot_device get_boot_device(void)
  287. {
  288. volatile gd_t *pgd = gd;
  289. int ret;
  290. u32 boot;
  291. u16 boot_type;
  292. u8 boot_instance;
  293. enum boot_device boot_dev = SD1_BOOT;
  294. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  295. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  296. gd = pgd;
  297. if (ret != ROM_API_OKAY) {
  298. puts("ROMAPI: failure at query_boot_info\n");
  299. return -1;
  300. }
  301. boot_type = boot >> 16;
  302. boot_instance = (boot >> 8) & 0xff;
  303. switch (boot_type) {
  304. case BT_DEV_TYPE_SD:
  305. boot_dev = boot_instance + SD1_BOOT;
  306. break;
  307. case BT_DEV_TYPE_MMC:
  308. boot_dev = boot_instance + MMC1_BOOT;
  309. break;
  310. case BT_DEV_TYPE_NAND:
  311. boot_dev = NAND_BOOT;
  312. break;
  313. case BT_DEV_TYPE_FLEXSPINOR:
  314. boot_dev = QSPI_BOOT;
  315. break;
  316. case BT_DEV_TYPE_USB:
  317. boot_dev = USB_BOOT;
  318. break;
  319. default:
  320. break;
  321. }
  322. return boot_dev;
  323. }
  324. #endif
  325. bool is_usb_boot(void)
  326. {
  327. return get_boot_device() == USB_BOOT;
  328. }
  329. #ifdef CONFIG_OF_SYSTEM_SETUP
  330. int ft_system_setup(void *blob, bd_t *bd)
  331. {
  332. int i = 0;
  333. int rc;
  334. int nodeoff;
  335. /* Disable the CPU idle for A0 chip since the HW does not support it */
  336. if (is_soc_rev(CHIP_REV_1_0)) {
  337. static const char * const nodes_path[] = {
  338. "/cpus/cpu@0",
  339. "/cpus/cpu@1",
  340. "/cpus/cpu@2",
  341. "/cpus/cpu@3",
  342. };
  343. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  344. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  345. if (nodeoff < 0)
  346. continue; /* Not found, skip it */
  347. debug("Found %s node\n", nodes_path[i]);
  348. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  349. if (rc == -FDT_ERR_NOTFOUND)
  350. continue;
  351. if (rc) {
  352. printf("Unable to update property %s:%s, err=%s\n",
  353. nodes_path[i], "status", fdt_strerror(rc));
  354. return rc;
  355. }
  356. debug("Remove %s:%s\n", nodes_path[i],
  357. "cpu-idle-states");
  358. }
  359. }
  360. return 0;
  361. }
  362. #endif
  363. #if !CONFIG_IS_ENABLED(SYSRESET)
  364. void reset_cpu(ulong addr)
  365. {
  366. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  367. /* Clear WDA to trigger WDOG_B immediately */
  368. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  369. while (1) {
  370. /*
  371. * spin for .5 seconds before reset
  372. */
  373. }
  374. }
  375. #endif
  376. #if defined(CONFIG_ARCH_MISC_INIT)
  377. static void acquire_buildinfo(void)
  378. {
  379. u64 atf_commit = 0;
  380. /* Get ARM Trusted Firmware commit id */
  381. atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
  382. IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
  383. if (atf_commit == 0xffffffff) {
  384. debug("ATF does not support build info\n");
  385. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  386. }
  387. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  388. }
  389. int arch_misc_init(void)
  390. {
  391. acquire_buildinfo();
  392. return 0;
  393. }
  394. #endif
  395. void imx_tmu_arch_init(void *reg_base)
  396. {
  397. if (is_imx8mm() || is_imx8mn()) {
  398. /* Load TCALIV and TASR from fuses */
  399. struct ocotp_regs *ocotp =
  400. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  401. struct fuse_bank *bank = &ocotp->bank[3];
  402. struct fuse_bank3_regs *fuse =
  403. (struct fuse_bank3_regs *)bank->fuse_regs;
  404. u32 tca_rt, tca_hr, tca_en;
  405. u32 buf_vref, buf_slope;
  406. tca_rt = fuse->ana0 & 0xFF;
  407. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  408. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  409. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  410. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  411. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  412. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  413. (ulong)reg_base + 0x30);
  414. }
  415. #ifdef CONFIG_IMX8MP
  416. /* Load TCALIV0/1/m40 and TRIM from fuses */
  417. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  418. struct fuse_bank *bank = &ocotp->bank[38];
  419. struct fuse_bank38_regs *fuse =
  420. (struct fuse_bank38_regs *)bank->fuse_regs;
  421. struct fuse_bank *bank2 = &ocotp->bank[39];
  422. struct fuse_bank39_regs *fuse2 =
  423. (struct fuse_bank39_regs *)bank2->fuse_regs;
  424. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  425. u32 reg;
  426. u32 tca40[2], tca25[2], tca105[2];
  427. /* For blank sample */
  428. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  429. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  430. /* Use a default 25C binary codes */
  431. tca25[0] = 1596;
  432. tca25[1] = 1596;
  433. writel(tca25[0], (ulong)reg_base + 0x30);
  434. writel(tca25[1], (ulong)reg_base + 0x34);
  435. return;
  436. }
  437. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  438. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  439. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  440. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  441. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  442. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  443. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  444. writel(reg, (ulong)reg_base + 0x3c);
  445. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  446. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  447. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  448. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  449. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  450. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  451. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  452. /* use 25c for 1p calibration */
  453. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  454. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  455. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  456. #endif
  457. }