cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <bootm.h>
  9. #include <common.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <imx_thermal.h>
  21. #include <ipu_pixfmt.h>
  22. #include <thermal.h>
  23. #include <sata.h>
  24. #ifdef CONFIG_FSL_ESDHC_IMX
  25. #include <fsl_esdhc_imx.h>
  26. #endif
  27. static u32 reset_cause = -1;
  28. u32 get_imx_reset_cause(void)
  29. {
  30. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  31. if (reset_cause == -1) {
  32. reset_cause = readl(&src_regs->srsr);
  33. /* preserve the value for U-Boot proper */
  34. #if !defined(CONFIG_SPL_BUILD)
  35. writel(reset_cause, &src_regs->srsr);
  36. #endif
  37. }
  38. return reset_cause;
  39. }
  40. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  41. static char *get_reset_cause(void)
  42. {
  43. switch (get_imx_reset_cause()) {
  44. case 0x00001:
  45. case 0x00011:
  46. return "POR";
  47. case 0x00004:
  48. return "CSU";
  49. case 0x00008:
  50. return "IPP USER";
  51. case 0x00010:
  52. #ifdef CONFIG_MX7
  53. return "WDOG1";
  54. #else
  55. return "WDOG";
  56. #endif
  57. case 0x00020:
  58. return "JTAG HIGH-Z";
  59. case 0x00040:
  60. return "JTAG SW";
  61. case 0x00080:
  62. return "WDOG3";
  63. #ifdef CONFIG_MX7
  64. case 0x00100:
  65. return "WDOG4";
  66. case 0x00200:
  67. return "TEMPSENSE";
  68. #elif defined(CONFIG_IMX8M)
  69. case 0x00100:
  70. return "WDOG2";
  71. case 0x00200:
  72. return "TEMPSENSE";
  73. #else
  74. case 0x00100:
  75. return "TEMPSENSE";
  76. case 0x10000:
  77. return "WARM BOOT";
  78. #endif
  79. default:
  80. return "unknown reset";
  81. }
  82. }
  83. #endif
  84. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  85. const char *get_imx_type(u32 imxtype)
  86. {
  87. switch (imxtype) {
  88. case MXC_CPU_IMX8MP:
  89. return "8MP"; /* Quad-core version of the imx8mp */
  90. case MXC_CPU_IMX8MN:
  91. return "8MNano Quad"; /* Quad-core version */
  92. case MXC_CPU_IMX8MND:
  93. return "8MNano Dual"; /* Dual-core version */
  94. case MXC_CPU_IMX8MNS:
  95. return "8MNano Solo"; /* Single-core version */
  96. case MXC_CPU_IMX8MNL:
  97. return "8MNano QuadLite"; /* Quad-core Lite version */
  98. case MXC_CPU_IMX8MNDL:
  99. return "8MNano DualLite"; /* Dual-core Lite version */
  100. case MXC_CPU_IMX8MNSL:
  101. return "8MNano SoloLite"; /* Single-core Lite version */
  102. case MXC_CPU_IMX8MM:
  103. return "8MMQ"; /* Quad-core version of the imx8mm */
  104. case MXC_CPU_IMX8MML:
  105. return "8MMQL"; /* Quad-core Lite version of the imx8mm */
  106. case MXC_CPU_IMX8MMD:
  107. return "8MMD"; /* Dual-core version of the imx8mm */
  108. case MXC_CPU_IMX8MMDL:
  109. return "8MMDL"; /* Dual-core Lite version of the imx8mm */
  110. case MXC_CPU_IMX8MMS:
  111. return "8MMS"; /* Single-core version of the imx8mm */
  112. case MXC_CPU_IMX8MMSL:
  113. return "8MMSL"; /* Single-core Lite version of the imx8mm */
  114. case MXC_CPU_IMX8MQ:
  115. return "8MQ"; /* Quad-core version of the imx8mq */
  116. case MXC_CPU_IMX8MQL:
  117. return "8MQLite"; /* Quad-core Lite version of the imx8mq */
  118. case MXC_CPU_IMX8MD:
  119. return "8MD"; /* Dual-core version of the imx8mq */
  120. case MXC_CPU_MX7S:
  121. return "7S"; /* Single-core version of the mx7 */
  122. case MXC_CPU_MX7D:
  123. return "7D"; /* Dual-core version of the mx7 */
  124. case MXC_CPU_MX6QP:
  125. return "6QP"; /* Quad-Plus version of the mx6 */
  126. case MXC_CPU_MX6DP:
  127. return "6DP"; /* Dual-Plus version of the mx6 */
  128. case MXC_CPU_MX6Q:
  129. return "6Q"; /* Quad-core version of the mx6 */
  130. case MXC_CPU_MX6D:
  131. return "6D"; /* Dual-core version of the mx6 */
  132. case MXC_CPU_MX6DL:
  133. return "6DL"; /* Dual Lite version of the mx6 */
  134. case MXC_CPU_MX6SOLO:
  135. return "6SOLO"; /* Solo version of the mx6 */
  136. case MXC_CPU_MX6SL:
  137. return "6SL"; /* Solo-Lite version of the mx6 */
  138. case MXC_CPU_MX6SLL:
  139. return "6SLL"; /* SLL version of the mx6 */
  140. case MXC_CPU_MX6SX:
  141. return "6SX"; /* SoloX version of the mx6 */
  142. case MXC_CPU_MX6UL:
  143. return "6UL"; /* Ultra-Lite version of the mx6 */
  144. case MXC_CPU_MX6ULL:
  145. return "6ULL"; /* ULL version of the mx6 */
  146. case MXC_CPU_MX6ULZ:
  147. return "6ULZ"; /* ULZ version of the mx6 */
  148. case MXC_CPU_MX51:
  149. return "51";
  150. case MXC_CPU_MX53:
  151. return "53";
  152. default:
  153. return "??";
  154. }
  155. }
  156. int print_cpuinfo(void)
  157. {
  158. u32 cpurev;
  159. __maybe_unused u32 max_freq;
  160. cpurev = get_cpu_rev();
  161. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  162. struct udevice *thermal_dev;
  163. int cpu_tmp, minc, maxc, ret;
  164. printf("CPU: Freescale i.MX%s rev%d.%d",
  165. get_imx_type((cpurev & 0x1FF000) >> 12),
  166. (cpurev & 0x000F0) >> 4,
  167. (cpurev & 0x0000F) >> 0);
  168. max_freq = get_cpu_speed_grade_hz();
  169. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  170. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  171. } else {
  172. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  173. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  174. }
  175. #else
  176. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  177. get_imx_type((cpurev & 0x1FF000) >> 12),
  178. (cpurev & 0x000F0) >> 4,
  179. (cpurev & 0x0000F) >> 0,
  180. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  181. #endif
  182. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  183. puts("CPU: ");
  184. switch (get_cpu_temp_grade(&minc, &maxc)) {
  185. case TEMP_AUTOMOTIVE:
  186. puts("Automotive temperature grade ");
  187. break;
  188. case TEMP_INDUSTRIAL:
  189. puts("Industrial temperature grade ");
  190. break;
  191. case TEMP_EXTCOMMERCIAL:
  192. puts("Extended Commercial temperature grade ");
  193. break;
  194. default:
  195. puts("Commercial temperature grade ");
  196. break;
  197. }
  198. printf("(%dC to %dC)", minc, maxc);
  199. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  200. if (!ret) {
  201. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  202. if (!ret)
  203. printf(" at %dC\n", cpu_tmp);
  204. else
  205. debug(" - invalid sensor data\n");
  206. } else {
  207. debug(" - invalid sensor device\n");
  208. }
  209. #endif
  210. printf("Reset cause: %s\n", get_reset_cause());
  211. return 0;
  212. }
  213. #endif
  214. int cpu_eth_init(bd_t *bis)
  215. {
  216. int rc = -ENODEV;
  217. #if defined(CONFIG_FEC_MXC)
  218. rc = fecmxc_initialize(bis);
  219. #endif
  220. return rc;
  221. }
  222. #ifdef CONFIG_FSL_ESDHC_IMX
  223. /*
  224. * Initializes on-chip MMC controllers.
  225. * to override, implement board_mmc_init()
  226. */
  227. int cpu_mmc_init(bd_t *bis)
  228. {
  229. return fsl_esdhc_mmc_init(bis);
  230. }
  231. #endif
  232. #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
  233. u32 get_ahb_clk(void)
  234. {
  235. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  236. u32 reg, ahb_podf;
  237. reg = __raw_readl(&imx_ccm->cbcdr);
  238. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  239. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  240. return get_periph_clk() / (ahb_podf + 1);
  241. }
  242. #endif
  243. void arch_preboot_os(void)
  244. {
  245. #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
  246. imx_pcie_remove();
  247. #endif
  248. #if defined(CONFIG_SATA)
  249. if (!is_mx6sdl()) {
  250. sata_remove(0);
  251. #if defined(CONFIG_MX6)
  252. disable_sata_clock();
  253. #endif
  254. }
  255. #endif
  256. #if defined(CONFIG_VIDEO_IPUV3)
  257. /* disable video before launching O/S */
  258. ipuv3_fb_shutdown();
  259. #endif
  260. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  261. lcdif_power_down();
  262. #endif
  263. }
  264. #ifndef CONFIG_IMX8M
  265. void set_chipselect_size(int const cs_size)
  266. {
  267. unsigned int reg;
  268. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  269. reg = readl(&iomuxc_regs->gpr[1]);
  270. switch (cs_size) {
  271. case CS0_128:
  272. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  273. reg |= 0x5;
  274. break;
  275. case CS0_64M_CS1_64M:
  276. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  277. reg |= 0x1B;
  278. break;
  279. case CS0_64M_CS1_32M_CS2_32M:
  280. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  281. reg |= 0x4B;
  282. break;
  283. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  284. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  285. reg |= 0x249;
  286. break;
  287. default:
  288. printf("Unknown chip select size: %d\n", cs_size);
  289. break;
  290. }
  291. writel(reg, &iomuxc_regs->gpr[1]);
  292. }
  293. #endif
  294. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  295. /*
  296. * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  297. * defines a 2-bit SPEED_GRADING
  298. */
  299. #define OCOTP_TESTER3_SPEED_SHIFT 8
  300. enum cpu_speed {
  301. OCOTP_TESTER3_SPEED_GRADE0,
  302. OCOTP_TESTER3_SPEED_GRADE1,
  303. OCOTP_TESTER3_SPEED_GRADE2,
  304. OCOTP_TESTER3_SPEED_GRADE3,
  305. OCOTP_TESTER3_SPEED_GRADE4,
  306. };
  307. u32 get_cpu_speed_grade_hz(void)
  308. {
  309. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  310. struct fuse_bank *bank = &ocotp->bank[1];
  311. struct fuse_bank1_regs *fuse =
  312. (struct fuse_bank1_regs *)bank->fuse_regs;
  313. uint32_t val;
  314. val = readl(&fuse->tester3);
  315. val >>= OCOTP_TESTER3_SPEED_SHIFT;
  316. if (is_imx8mn() || is_imx8mp()) {
  317. val &= 0xf;
  318. return 2300000000 - val * 100000000;
  319. }
  320. if (is_imx8mm())
  321. val &= 0x7;
  322. else
  323. val &= 0x3;
  324. switch(val) {
  325. case OCOTP_TESTER3_SPEED_GRADE0:
  326. return 800000000;
  327. case OCOTP_TESTER3_SPEED_GRADE1:
  328. return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
  329. case OCOTP_TESTER3_SPEED_GRADE2:
  330. return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
  331. case OCOTP_TESTER3_SPEED_GRADE3:
  332. return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
  333. case OCOTP_TESTER3_SPEED_GRADE4:
  334. return 2000000000;
  335. }
  336. return 0;
  337. }
  338. /*
  339. * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  340. * defines a 2-bit SPEED_GRADING
  341. */
  342. #define OCOTP_TESTER3_TEMP_SHIFT 6
  343. u32 get_cpu_temp_grade(int *minc, int *maxc)
  344. {
  345. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  346. struct fuse_bank *bank = &ocotp->bank[1];
  347. struct fuse_bank1_regs *fuse =
  348. (struct fuse_bank1_regs *)bank->fuse_regs;
  349. uint32_t val;
  350. val = readl(&fuse->tester3);
  351. val >>= OCOTP_TESTER3_TEMP_SHIFT;
  352. val &= 0x3;
  353. if (minc && maxc) {
  354. if (val == TEMP_AUTOMOTIVE) {
  355. *minc = -40;
  356. *maxc = 125;
  357. } else if (val == TEMP_INDUSTRIAL) {
  358. *minc = -40;
  359. *maxc = 105;
  360. } else if (val == TEMP_EXTCOMMERCIAL) {
  361. *minc = -20;
  362. *maxc = 105;
  363. } else {
  364. *minc = 0;
  365. *maxc = 95;
  366. }
  367. }
  368. return val;
  369. }
  370. #endif
  371. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
  372. enum boot_device get_boot_device(void)
  373. {
  374. struct bootrom_sw_info **p =
  375. (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
  376. enum boot_device boot_dev = SD1_BOOT;
  377. u8 boot_type = (*p)->boot_dev_type;
  378. u8 boot_instance = (*p)->boot_dev_instance;
  379. switch (boot_type) {
  380. case BOOT_TYPE_SD:
  381. boot_dev = boot_instance + SD1_BOOT;
  382. break;
  383. case BOOT_TYPE_MMC:
  384. boot_dev = boot_instance + MMC1_BOOT;
  385. break;
  386. case BOOT_TYPE_NAND:
  387. boot_dev = NAND_BOOT;
  388. break;
  389. case BOOT_TYPE_QSPI:
  390. boot_dev = QSPI_BOOT;
  391. break;
  392. case BOOT_TYPE_WEIM:
  393. boot_dev = WEIM_NOR_BOOT;
  394. break;
  395. case BOOT_TYPE_SPINOR:
  396. boot_dev = SPI_NOR_BOOT;
  397. break;
  398. #ifdef CONFIG_IMX8M
  399. case BOOT_TYPE_USB:
  400. boot_dev = USB_BOOT;
  401. break;
  402. #endif
  403. default:
  404. break;
  405. }
  406. return boot_dev;
  407. }
  408. #endif
  409. #ifdef CONFIG_NXP_BOARD_REVISION
  410. int nxp_board_rev(void)
  411. {
  412. /*
  413. * Get Board ID information from OCOTP_GP1[15:8]
  414. * RevA: 0x1
  415. * RevB: 0x2
  416. * RevC: 0x3
  417. */
  418. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  419. struct fuse_bank *bank = &ocotp->bank[4];
  420. struct fuse_bank4_regs *fuse =
  421. (struct fuse_bank4_regs *)bank->fuse_regs;
  422. return (readl(&fuse->gp1) >> 8 & 0x0F);
  423. }
  424. char nxp_board_rev_string(void)
  425. {
  426. const char *rev = "A";
  427. return (*rev + nxp_board_rev() - 1);
  428. }
  429. #endif