timer.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Texas Instruments <www.ti.com>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Marius Groeger <mgroeger@sysgo.de>
  9. *
  10. * (C) Copyright 2002
  11. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12. * Alex Zuepke <azu@sysgo.de>
  13. *
  14. * (C) Copyright 2002-2004
  15. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16. *
  17. * (C) Copyright 2004
  18. * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  19. *
  20. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  21. */
  22. #include <common.h>
  23. #include <init.h>
  24. #include <time.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/timer_defs.h>
  27. #include <div64.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static struct davinci_timer * const timer =
  30. (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
  31. #define TIMER_LOAD_VAL 0xffffffff
  32. #define TIM_CLK_DIV 16
  33. int timer_init(void)
  34. {
  35. /* We are using timer34 in unchained 32-bit mode, full speed */
  36. writel(0x0, &timer->tcr);
  37. writel(0x0, &timer->tgcr);
  38. writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
  39. writel(0x0, &timer->tim34);
  40. writel(TIMER_LOAD_VAL, &timer->prd34);
  41. writel(2 << 22, &timer->tcr);
  42. gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
  43. gd->arch.timer_reset_value = 0;
  44. return(0);
  45. }
  46. /*
  47. * Get the current 64 bit timer tick count
  48. */
  49. unsigned long long get_ticks(void)
  50. {
  51. unsigned long now = readl(&timer->tim34);
  52. /* increment tbu if tbl has rolled over */
  53. if (now < gd->arch.tbl)
  54. gd->arch.tbu++;
  55. gd->arch.tbl = now;
  56. return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  57. }
  58. ulong get_timer(ulong base)
  59. {
  60. unsigned long long timer_diff;
  61. timer_diff = get_ticks() - gd->arch.timer_reset_value;
  62. return lldiv(timer_diff,
  63. (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
  64. }
  65. void __udelay(unsigned long usec)
  66. {
  67. unsigned long long endtime;
  68. endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
  69. 1000000UL);
  70. endtime += get_ticks();
  71. while (get_ticks() < endtime)
  72. ;
  73. }
  74. /*
  75. * This function is derived from PowerPC code (timebase clock frequency).
  76. * On ARM it returns the number of timer ticks per second.
  77. */
  78. ulong get_tbclk(void)
  79. {
  80. return gd->arch.timer_rate_hz;
  81. }
  82. #ifdef CONFIG_HW_WATCHDOG
  83. static struct davinci_timer * const wdttimer =
  84. (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
  85. /*
  86. * See prufw2.pdf for using Timer as a WDT
  87. */
  88. void davinci_hw_watchdog_enable(void)
  89. {
  90. writel(0x0, &wdttimer->tcr);
  91. writel(0x0, &wdttimer->tgcr);
  92. /* TIMMODE = 2h */
  93. writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
  94. writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
  95. writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
  96. writel(2 << 22, &wdttimer->tcr);
  97. writel(0x0, &wdttimer->tim12);
  98. writel(0x0, &wdttimer->tim34);
  99. /* set WDEN bit, WDKEY 0xa5c6 */
  100. writel(0xa5c64000, &wdttimer->wdtcr);
  101. /* clear counter register */
  102. writel(0xda7e4000, &wdttimer->wdtcr);
  103. }
  104. void davinci_hw_watchdog_reset(void)
  105. {
  106. writel(0xa5c64000, &wdttimer->wdtcr);
  107. writel(0xda7e4000, &wdttimer->wdtcr);
  108. }
  109. #endif