generic.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/mach-imx/sys_proto.h>
  16. #include <env.h>
  17. #include <netdev.h>
  18. #ifdef CONFIG_FSL_ESDHC_IMX
  19. #include <fsl_esdhc_imx.h>
  20. #endif
  21. #ifdef CONFIG_FSL_ESDHC_IMX
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #endif
  24. static char soc_type[] = "xx0";
  25. #ifdef CONFIG_MXC_OCOTP
  26. void enable_ocotp_clk(unsigned char enable)
  27. {
  28. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  29. u32 reg;
  30. reg = readl(&ccm->ccgr6);
  31. if (enable)
  32. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  33. else
  34. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  35. writel(reg, &ccm->ccgr6);
  36. }
  37. #endif
  38. static u32 get_mcu_main_clk(void)
  39. {
  40. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  41. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  42. u32 sysclk_sel, pll_pfd_sel = 0;
  43. u32 freq = 0;
  44. ccm_ccsr = readl(&ccm->ccsr);
  45. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  46. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  47. ccm_cacrr = readl(&ccm->cacrr);
  48. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  49. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  50. armclk_div += 1;
  51. switch (sysclk_sel) {
  52. case 0:
  53. freq = FASE_CLK_FREQ;
  54. break;
  55. case 1:
  56. freq = SLOW_CLK_FREQ;
  57. break;
  58. case 2:
  59. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  60. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  61. if (pll_pfd_sel == 0)
  62. freq = PLL2_MAIN_FREQ;
  63. else if (pll_pfd_sel == 1)
  64. freq = PLL2_PFD1_FREQ;
  65. else if (pll_pfd_sel == 2)
  66. freq = PLL2_PFD2_FREQ;
  67. else if (pll_pfd_sel == 3)
  68. freq = PLL2_PFD3_FREQ;
  69. else if (pll_pfd_sel == 4)
  70. freq = PLL2_PFD4_FREQ;
  71. break;
  72. case 3:
  73. freq = PLL2_MAIN_FREQ;
  74. break;
  75. case 4:
  76. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  77. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  78. if (pll_pfd_sel == 0)
  79. freq = PLL1_MAIN_FREQ;
  80. else if (pll_pfd_sel == 1)
  81. freq = PLL1_PFD1_FREQ;
  82. else if (pll_pfd_sel == 2)
  83. freq = PLL1_PFD2_FREQ;
  84. else if (pll_pfd_sel == 3)
  85. freq = PLL1_PFD3_FREQ;
  86. else if (pll_pfd_sel == 4)
  87. freq = PLL1_PFD4_FREQ;
  88. break;
  89. case 5:
  90. freq = PLL3_MAIN_FREQ;
  91. break;
  92. default:
  93. printf("unsupported system clock select\n");
  94. }
  95. return freq / armclk_div;
  96. }
  97. static u32 get_bus_clk(void)
  98. {
  99. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  100. u32 ccm_cacrr, busclk_div;
  101. ccm_cacrr = readl(&ccm->cacrr);
  102. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  103. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  104. busclk_div += 1;
  105. return get_mcu_main_clk() / busclk_div;
  106. }
  107. static u32 get_ipg_clk(void)
  108. {
  109. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  110. u32 ccm_cacrr, ipgclk_div;
  111. ccm_cacrr = readl(&ccm->cacrr);
  112. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  113. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  114. ipgclk_div += 1;
  115. return get_bus_clk() / ipgclk_div;
  116. }
  117. static u32 get_uart_clk(void)
  118. {
  119. return get_ipg_clk();
  120. }
  121. static u32 get_sdhc_clk(void)
  122. {
  123. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  124. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  125. u32 freq = 0;
  126. ccm_cscmr1 = readl(&ccm->cscmr1);
  127. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  128. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  129. ccm_cscdr2 = readl(&ccm->cscdr2);
  130. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  131. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  132. sdhc_clk_div += 1;
  133. switch (sdhc_clk_sel) {
  134. case 0:
  135. freq = PLL3_MAIN_FREQ;
  136. break;
  137. case 1:
  138. freq = PLL3_PFD3_FREQ;
  139. break;
  140. case 2:
  141. freq = PLL1_PFD3_FREQ;
  142. break;
  143. case 3:
  144. freq = get_bus_clk();
  145. break;
  146. }
  147. return freq / sdhc_clk_div;
  148. }
  149. u32 get_fec_clk(void)
  150. {
  151. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  152. u32 ccm_cscmr2, rmii_clk_sel;
  153. u32 freq = 0;
  154. ccm_cscmr2 = readl(&ccm->cscmr2);
  155. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  156. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  157. switch (rmii_clk_sel) {
  158. case 0:
  159. freq = ENET_EXTERNAL_CLK;
  160. break;
  161. case 1:
  162. freq = AUDIO_EXTERNAL_CLK;
  163. break;
  164. case 2:
  165. freq = PLL5_MAIN_FREQ;
  166. break;
  167. case 3:
  168. freq = PLL5_MAIN_FREQ / 2;
  169. break;
  170. }
  171. return freq;
  172. }
  173. static u32 get_i2c_clk(void)
  174. {
  175. return get_ipg_clk();
  176. }
  177. static u32 get_dspi_clk(void)
  178. {
  179. return get_ipg_clk();
  180. }
  181. u32 get_lpuart_clk(void)
  182. {
  183. return get_uart_clk();
  184. }
  185. unsigned int mxc_get_clock(enum mxc_clock clk)
  186. {
  187. switch (clk) {
  188. case MXC_ARM_CLK:
  189. return get_mcu_main_clk();
  190. case MXC_BUS_CLK:
  191. return get_bus_clk();
  192. case MXC_IPG_CLK:
  193. return get_ipg_clk();
  194. case MXC_UART_CLK:
  195. return get_uart_clk();
  196. case MXC_ESDHC_CLK:
  197. return get_sdhc_clk();
  198. case MXC_FEC_CLK:
  199. return get_fec_clk();
  200. case MXC_I2C_CLK:
  201. return get_i2c_clk();
  202. case MXC_DSPI_CLK:
  203. return get_dspi_clk();
  204. default:
  205. break;
  206. }
  207. return -1;
  208. }
  209. /* Dump some core clocks */
  210. int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  211. char * const argv[])
  212. {
  213. printf("\n");
  214. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  215. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  216. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  217. return 0;
  218. }
  219. U_BOOT_CMD(
  220. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  221. "display clocks",
  222. ""
  223. );
  224. #ifdef CONFIG_FEC_MXC
  225. __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  226. {
  227. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  228. struct fuse_bank *bank = &ocotp->bank[4];
  229. struct fuse_bank4_regs *fuse =
  230. (struct fuse_bank4_regs *)bank->fuse_regs;
  231. u32 value = readl(&fuse->mac_addr0);
  232. mac[0] = (value >> 8);
  233. mac[1] = value;
  234. value = readl(&fuse->mac_addr1);
  235. mac[2] = value >> 24;
  236. mac[3] = value >> 16;
  237. mac[4] = value >> 8;
  238. mac[5] = value;
  239. }
  240. #endif
  241. u32 get_cpu_rev(void)
  242. {
  243. return MXC_CPU_VF610 << 12;
  244. }
  245. #if defined(CONFIG_DISPLAY_CPUINFO)
  246. static char *get_reset_cause(void)
  247. {
  248. u32 cause;
  249. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  250. cause = readl(&src_regs->srsr);
  251. writel(cause, &src_regs->srsr);
  252. if (cause & SRC_SRSR_POR_RST)
  253. return "POWER ON RESET";
  254. else if (cause & SRC_SRSR_WDOG_A5)
  255. return "WDOG A5";
  256. else if (cause & SRC_SRSR_WDOG_M4)
  257. return "WDOG M4";
  258. else if (cause & SRC_SRSR_JTAG_RST)
  259. return "JTAG HIGH-Z";
  260. else if (cause & SRC_SRSR_SW_RST)
  261. return "SW RESET";
  262. else if (cause & SRC_SRSR_RESETB)
  263. return "EXTERNAL RESET";
  264. else
  265. return "unknown reset";
  266. }
  267. int print_cpuinfo(void)
  268. {
  269. printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
  270. soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
  271. printf("Reset cause: %s\n", get_reset_cause());
  272. return 0;
  273. }
  274. #endif
  275. int arch_cpu_init(void)
  276. {
  277. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  278. soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
  279. soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
  280. return 0;
  281. }
  282. #ifdef CONFIG_ARCH_MISC_INIT
  283. int arch_misc_init(void)
  284. {
  285. char soc[6];
  286. strcpy(soc, "vf");
  287. strcat(soc, soc_type);
  288. env_set("soc", soc);
  289. return 0;
  290. }
  291. #endif
  292. int cpu_eth_init(bd_t *bis)
  293. {
  294. int rc = -ENODEV;
  295. #if defined(CONFIG_FEC_MXC)
  296. rc = fecmxc_initialize(bis);
  297. #endif
  298. return rc;
  299. }
  300. #ifdef CONFIG_FSL_ESDHC_IMX
  301. int cpu_mmc_init(bd_t *bis)
  302. {
  303. return fsl_esdhc_mmc_init(bis);
  304. }
  305. #endif
  306. int get_clocks(void)
  307. {
  308. #ifdef CONFIG_FSL_ESDHC_IMX
  309. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  310. #endif
  311. return 0;
  312. }
  313. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  314. void enable_caches(void)
  315. {
  316. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  317. enum dcache_option option = DCACHE_WRITETHROUGH;
  318. #else
  319. enum dcache_option option = DCACHE_WRITEBACK;
  320. #endif
  321. dcache_enable();
  322. icache_enable();
  323. /* Enable caching on OCRAM */
  324. mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
  325. }
  326. #endif
  327. #ifdef CONFIG_SYS_I2C_MXC
  328. /* i2c_num can be from 0 - 3 */
  329. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  330. {
  331. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  332. switch (i2c_num) {
  333. case 0:
  334. clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
  335. CCM_CCGR4_I2C0_CTRL_MASK);
  336. case 2:
  337. clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
  338. CCM_CCGR10_I2C2_CTRL_MASK);
  339. break;
  340. default:
  341. return -EINVAL;
  342. }
  343. return 0;
  344. }
  345. #endif