cpu.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <vsprintf.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/immap_ls102xa.h>
  13. #include <asm/cache.h>
  14. #include <asm/system.h>
  15. #include <tsec.h>
  16. #include <netdev.h>
  17. #include <fsl_esdhc.h>
  18. #include <config.h>
  19. #include <fsl_wdog.h>
  20. #include "fsl_epu.h"
  21. #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
  22. #define DCSR_RCPM2_CPMFSMCR0 0x400
  23. #define DCSR_RCPM2_CPMFSMSR0 0x404
  24. #define DCSR_RCPM2_CPMFSMCR1 0x414
  25. #define DCSR_RCPM2_CPMFSMSR1 0x418
  26. #define CPMFSMSR_FSM_STATE_MASK 0x7f
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  29. /*
  30. * Bit[1] of the descriptor indicates the descriptor type,
  31. * and bit[0] indicates whether the descriptor is valid.
  32. */
  33. #define PMD_TYPE_TABLE 0x3
  34. #define PMD_TYPE_SECT 0x1
  35. /* AttrIndx[2:0] */
  36. #define PMD_ATTRINDX(t) ((t) << 2)
  37. /* Section */
  38. #define PMD_SECT_AF (1 << 10)
  39. #define BLOCK_SIZE_L1 (1UL << 30)
  40. #define BLOCK_SIZE_L2 (1UL << 21)
  41. /* TTBCR flags */
  42. #define TTBCR_EAE (1 << 31)
  43. #define TTBCR_T0SZ(x) ((x) << 0)
  44. #define TTBCR_T1SZ(x) ((x) << 16)
  45. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  46. #define TTBCR_IRGN0_NC (0 << 8)
  47. #define TTBCR_IRGN0_WBWA (1 << 8)
  48. #define TTBCR_IRGN0_WT (2 << 8)
  49. #define TTBCR_IRGN0_WBNWA (3 << 8)
  50. #define TTBCR_IRGN0_MASK (3 << 8)
  51. #define TTBCR_ORGN0_NC (0 << 10)
  52. #define TTBCR_ORGN0_WBWA (1 << 10)
  53. #define TTBCR_ORGN0_WT (2 << 10)
  54. #define TTBCR_ORGN0_WBNWA (3 << 10)
  55. #define TTBCR_ORGN0_MASK (3 << 10)
  56. #define TTBCR_SHARED_NON (0 << 12)
  57. #define TTBCR_SHARED_OUTER (2 << 12)
  58. #define TTBCR_SHARED_INNER (3 << 12)
  59. #define TTBCR_EPD0 (0 << 7)
  60. #define TTBCR (TTBCR_SHARED_NON | \
  61. TTBCR_ORGN0_NC | \
  62. TTBCR_IRGN0_NC | \
  63. TTBCR_USING_TTBR0 | \
  64. TTBCR_EAE)
  65. /*
  66. * Memory region attributes for LPAE (defined in pgtable):
  67. *
  68. * n = AttrIndx[2:0]
  69. *
  70. * n MAIR
  71. * UNCACHED 000 00000000
  72. * BUFFERABLE 001 01000100
  73. * DEV_WC 001 01000100
  74. * WRITETHROUGH 010 10101010
  75. * WRITEBACK 011 11101110
  76. * DEV_CACHED 011 11101110
  77. * DEV_SHARED 100 00000100
  78. * DEV_NONSHARED 100 00000100
  79. * unused 101
  80. * unused 110
  81. * WRITEALLOC 111 11111111
  82. */
  83. #define MT_MAIR0 0xeeaa4400
  84. #define MT_MAIR1 0xff000004
  85. #define MT_STRONLY_ORDER 0
  86. #define MT_NORMAL_NC 1
  87. #define MT_DEVICE_MEM 4
  88. #define MT_NORMAL 7
  89. /* The phy_addr must be aligned to 4KB */
  90. static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
  91. {
  92. u32 value = phy_addr | PMD_TYPE_TABLE;
  93. page_table[2 * index] = value;
  94. page_table[2 * index + 1] = 0;
  95. }
  96. /* The phy_addr must be aligned to 4KB */
  97. static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
  98. u32 memory_type)
  99. {
  100. u64 value;
  101. value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
  102. value |= PMD_ATTRINDX(memory_type);
  103. page_table[2 * index] = value & 0xFFFFFFFF;
  104. page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
  105. }
  106. /*
  107. * Start MMU after DDR is available, we create MMU table in DRAM.
  108. * The base address of TTLB is gd->arch.tlb_addr. We use two
  109. * levels of translation tables here to cover 40-bit address space.
  110. *
  111. * The TTLBs are located at PHY 2G~4G.
  112. *
  113. * VA mapping:
  114. *
  115. * ------- <---- 0GB
  116. * | |
  117. * | |
  118. * |-------| <---- 0x24000000
  119. * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
  120. * |-------| <---- 0x300000000
  121. * | |
  122. * |-------| <---- 0x34000000
  123. * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
  124. * |-------| <---- 0x40000000
  125. * | |
  126. * |-------| <---- 0x80000000 DDR0 space start
  127. * |\\\\\\\|
  128. *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
  129. * |\\\\\\\|
  130. * ------- <---- 4GB DDR0 space end
  131. */
  132. static void mmu_setup(void)
  133. {
  134. u32 *level0_table = (u32 *)gd->arch.tlb_addr;
  135. u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
  136. u64 va_start = 0;
  137. u32 reg;
  138. int i;
  139. /* Level 0 Table 2-3 are used to map DDR */
  140. set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
  141. set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
  142. /* Level 0 Table 1 is used to map device */
  143. set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
  144. /* Level 0 Table 0 is used to map device including PCIe MEM */
  145. set_pgtable(level0_table, 0, (u32)level1_table);
  146. /* Level 1 has 512 entries */
  147. for (i = 0; i < 512; i++) {
  148. /* Mapping for PCIe 1 */
  149. if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
  150. va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
  151. CONFIG_SYS_PCIE_MMAP_SIZE))
  152. set_pgsection(level1_table, i,
  153. CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
  154. MT_DEVICE_MEM);
  155. /* Mapping for PCIe 2 */
  156. else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
  157. va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
  158. CONFIG_SYS_PCIE_MMAP_SIZE))
  159. set_pgsection(level1_table, i,
  160. CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
  161. MT_DEVICE_MEM);
  162. else
  163. set_pgsection(level1_table, i,
  164. va_start,
  165. MT_DEVICE_MEM);
  166. va_start += BLOCK_SIZE_L2;
  167. }
  168. asm volatile("dsb sy;isb");
  169. asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
  170. : : "r" (TTBCR) : "memory");
  171. asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
  172. : : "r" ((u32)level0_table), "r" (0) : "memory");
  173. asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
  174. : : "r" (MT_MAIR0) : "memory");
  175. asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
  176. : : "r" (MT_MAIR1) : "memory");
  177. /* Set the access control to all-supervisor */
  178. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  179. : : "r" (~0));
  180. /* Enable the mmu */
  181. reg = get_cr();
  182. set_cr(reg | CR_M);
  183. }
  184. /*
  185. * This function is called from lib/board.c. It recreates MMU
  186. * table in main memory. MMU and i/d-cache are enabled here.
  187. */
  188. void enable_caches(void)
  189. {
  190. /* Invalidate all TLB */
  191. mmu_page_table_flush(gd->arch.tlb_addr,
  192. gd->arch.tlb_addr + gd->arch.tlb_size);
  193. /* Set up and enable mmu */
  194. mmu_setup();
  195. /* Invalidate & Enable d-cache */
  196. invalidate_dcache_all();
  197. set_cr(get_cr() | CR_C);
  198. }
  199. #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  200. uint get_svr(void)
  201. {
  202. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  203. return in_be32(&gur->svr);
  204. }
  205. #if defined(CONFIG_DISPLAY_CPUINFO)
  206. int print_cpuinfo(void)
  207. {
  208. char buf1[32], buf2[32];
  209. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  210. unsigned int svr, major, minor, ver, i;
  211. svr = in_be32(&gur->svr);
  212. major = SVR_MAJ(svr);
  213. minor = SVR_MIN(svr);
  214. puts("CPU: Freescale LayerScape ");
  215. ver = SVR_SOC_VER(svr);
  216. switch (ver) {
  217. case SOC_VER_SLS1020:
  218. puts("SLS1020");
  219. break;
  220. case SOC_VER_LS1020:
  221. puts("LS1020");
  222. break;
  223. case SOC_VER_LS1021:
  224. puts("LS1021");
  225. break;
  226. case SOC_VER_LS1022:
  227. puts("LS1022");
  228. break;
  229. default:
  230. puts("Unknown");
  231. break;
  232. }
  233. if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
  234. puts("E");
  235. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  236. puts("Clock Configuration:");
  237. printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
  238. printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
  239. printf("DDR:%-4s MHz (%s MT/s data rate), ",
  240. strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
  241. puts("\n");
  242. /* Display the RCW, so that no one gets confused as to what RCW
  243. * we're actually using for this boot.
  244. */
  245. puts("Reset Configuration Word (RCW):");
  246. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  247. u32 rcw = in_be32(&gur->rcwsr[i]);
  248. if ((i % 4) == 0)
  249. printf("\n %08x:", i * 4);
  250. printf(" %08x", rcw);
  251. }
  252. puts("\n");
  253. return 0;
  254. }
  255. #endif
  256. #ifdef CONFIG_FSL_ESDHC
  257. int cpu_mmc_init(bd_t *bis)
  258. {
  259. return fsl_esdhc_mmc_init(bis);
  260. }
  261. #endif
  262. int cpu_eth_init(bd_t *bis)
  263. {
  264. #if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
  265. tsec_standard_init(bis);
  266. #endif
  267. return 0;
  268. }
  269. int arch_cpu_init(void)
  270. {
  271. void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  272. void *rcpm2_base =
  273. (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
  274. struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  275. u32 state;
  276. /*
  277. * The RCPM FSM state may not be reset after power-on.
  278. * So, reset them.
  279. */
  280. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
  281. CPMFSMSR_FSM_STATE_MASK;
  282. if (state != 0) {
  283. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
  284. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
  285. }
  286. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
  287. CPMFSMSR_FSM_STATE_MASK;
  288. if (state != 0) {
  289. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
  290. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
  291. }
  292. /*
  293. * After wakeup from deep sleep, Clear EPU registers
  294. * as early as possible to prevent from possible issue.
  295. * It's also safe to clear at normal boot.
  296. */
  297. fsl_epu_clean(epu_base);
  298. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
  299. return 0;
  300. }
  301. #ifdef CONFIG_ARMV7_NONSEC
  302. /* Set the address at which the secondary core starts from.*/
  303. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  304. {
  305. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  306. out_be32(&gur->scratchrw[0], addr);
  307. }
  308. /* Release the secondary core from holdoff state and kick it */
  309. void smp_kick_all_cpus(void)
  310. {
  311. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  312. out_be32(&gur->brrl, 0x2);
  313. /*
  314. * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
  315. * So add a delay to wait bootrom execute WFE.
  316. */
  317. udelay(1);
  318. asm volatile("sev");
  319. }
  320. #endif
  321. void reset_cpu(ulong addr)
  322. {
  323. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  324. clrbits_be16(&wdog->wcr, WCR_SRS);
  325. while (1) {
  326. /*
  327. * Let the watchdog trigger
  328. */
  329. }
  330. }
  331. void arch_preboot_os(void)
  332. {
  333. unsigned long ctrl;
  334. /* Disable PL1 Physical Timer */
  335. asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
  336. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  337. asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
  338. }