mxs.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 common code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <hang.h>
  14. #include <init.h>
  15. #include <net.h>
  16. #include <linux/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/mach-imx/dma.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/iomux.h>
  22. #include <asm/arch/imx-regs.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <linux/compiler.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
  27. __weak void lowlevel_init(void) {}
  28. void reset_cpu(ulong ignored) __attribute__((noreturn));
  29. void reset_cpu(ulong ignored)
  30. {
  31. struct mxs_rtc_regs *rtc_regs =
  32. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  33. struct mxs_lcdif_regs *lcdif_regs =
  34. (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  35. /*
  36. * Shut down the LCD controller as it interferes with BootROM boot mode
  37. * pads sampling.
  38. */
  39. writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
  40. /* Wait 1 uS before doing the actual watchdog reset */
  41. writel(1, &rtc_regs->hw_rtc_watchdog);
  42. writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
  43. /* Endless loop, reset will exit from here */
  44. for (;;)
  45. ;
  46. }
  47. /*
  48. * This function will craft a jumptable at 0x0 which will redirect interrupt
  49. * vectoring to proper location of U-Boot in RAM.
  50. *
  51. * The structure of the jumptable will be as follows:
  52. * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
  53. * <destination address> ... for each previous ldr, thus also repeated 8 times
  54. *
  55. * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
  56. * offset 0x18 from current value of PC register. Note that PC is already
  57. * incremented by 4 when computing the offset, so the effective offset is
  58. * actually 0x20, this the associated <destination address>. Loading the PC
  59. * register with an address performs a jump to that address.
  60. */
  61. void mx28_fixup_vt(uint32_t start_addr)
  62. {
  63. /* ldr pc, [pc, #0x18] */
  64. const uint32_t ldr_pc = 0xe59ff018;
  65. /* Jumptable location is 0x0 */
  66. uint32_t *vt = (uint32_t *)0x0;
  67. int i;
  68. for (i = 0; i < 8; i++) {
  69. /* cppcheck-suppress nullPointer */
  70. vt[i] = ldr_pc;
  71. /* cppcheck-suppress nullPointer */
  72. vt[i + 8] = start_addr + (4 * i);
  73. }
  74. }
  75. #ifdef CONFIG_ARCH_MISC_INIT
  76. int arch_misc_init(void)
  77. {
  78. mx28_fixup_vt(gd->relocaddr);
  79. return 0;
  80. }
  81. #endif
  82. int arch_cpu_init(void)
  83. {
  84. struct mxs_clkctrl_regs *clkctrl_regs =
  85. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  86. extern uint32_t _start;
  87. mx28_fixup_vt((uint32_t)&_start);
  88. /*
  89. * Enable NAND clock
  90. */
  91. /* Set bypass bit */
  92. writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
  93. &clkctrl_regs->hw_clkctrl_clkseq_set);
  94. /* Set GPMI clock to ref_xtal / 1 */
  95. clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
  96. while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
  97. ;
  98. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
  99. CLKCTRL_GPMI_DIV_MASK, 1);
  100. udelay(1000);
  101. /*
  102. * Configure GPIO unit
  103. */
  104. mxs_gpio_init();
  105. #ifdef CONFIG_APBH_DMA
  106. /* Start APBH DMA */
  107. mxs_dma_init();
  108. #endif
  109. return 0;
  110. }
  111. u32 get_cpu_rev(void)
  112. {
  113. struct mxs_digctl_regs *digctl_regs =
  114. (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
  115. uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
  116. switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
  117. case HW_DIGCTL_CHIPID_MX23:
  118. switch (rev) {
  119. case 0x0:
  120. case 0x1:
  121. case 0x2:
  122. case 0x3:
  123. case 0x4:
  124. return (MXC_CPU_MX23 << 12) | (rev + 0x10);
  125. default:
  126. return 0;
  127. }
  128. case HW_DIGCTL_CHIPID_MX28:
  129. switch (rev) {
  130. case 0x1:
  131. return (MXC_CPU_MX28 << 12) | 0x12;
  132. default:
  133. return 0;
  134. }
  135. default:
  136. return 0;
  137. }
  138. }
  139. #if defined(CONFIG_DISPLAY_CPUINFO)
  140. const char *get_imx_type(u32 imxtype)
  141. {
  142. switch (imxtype) {
  143. case MXC_CPU_MX23:
  144. return "23";
  145. case MXC_CPU_MX28:
  146. return "28";
  147. default:
  148. return "??";
  149. }
  150. }
  151. int print_cpuinfo(void)
  152. {
  153. u32 cpurev;
  154. struct mxs_spl_data *data = MXS_SPL_DATA;
  155. cpurev = get_cpu_rev();
  156. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  157. get_imx_type((cpurev & 0xFF000) >> 12),
  158. (cpurev & 0x000F0) >> 4,
  159. (cpurev & 0x0000F) >> 0,
  160. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  161. printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
  162. return 0;
  163. }
  164. #endif
  165. int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  166. {
  167. printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  168. printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
  169. printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
  170. printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
  171. return 0;
  172. }
  173. /*
  174. * Initializes on-chip ethernet controllers.
  175. */
  176. #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
  177. int cpu_eth_init(bd_t *bis)
  178. {
  179. struct mxs_clkctrl_regs *clkctrl_regs =
  180. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  181. /* Turn on ENET clocks */
  182. clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  183. CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
  184. /* Set up ENET PLL for 50 MHz */
  185. /* Power on ENET PLL */
  186. writel(CLKCTRL_PLL2CTRL0_POWER,
  187. &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
  188. udelay(10);
  189. /* Gate on ENET PLL */
  190. writel(CLKCTRL_PLL2CTRL0_CLKGATE,
  191. &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
  192. /* Enable pad output */
  193. setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
  194. return 0;
  195. }
  196. #endif
  197. __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
  198. {
  199. mac[0] = 0x00;
  200. mac[1] = 0x04; /* Use FSL vendor MAC address by default */
  201. if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
  202. mac[5] += 1;
  203. }
  204. #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
  205. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  206. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  207. {
  208. struct mxs_ocotp_regs *ocotp_regs =
  209. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  210. uint32_t data;
  211. memset(mac, 0, 6);
  212. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  213. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  214. MXS_OCOTP_MAX_TIMEOUT)) {
  215. printf("MXS FEC: Can't get MAC from OCOTP\n");
  216. return;
  217. }
  218. data = readl(&ocotp_regs->hw_ocotp_cust0);
  219. mac[2] = (data >> 24) & 0xff;
  220. mac[3] = (data >> 16) & 0xff;
  221. mac[4] = (data >> 8) & 0xff;
  222. mac[5] = data & 0xff;
  223. mx28_adjust_mac(dev_id, mac);
  224. }
  225. #else
  226. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  227. {
  228. memset(mac, 0, 6);
  229. }
  230. #endif
  231. int mxs_dram_init(void)
  232. {
  233. struct mxs_spl_data *data = MXS_SPL_DATA;
  234. if (data->mem_dram_size == 0) {
  235. printf("MXS:\n"
  236. "Error, the RAM size passed up from SPL is 0!\n");
  237. hang();
  238. }
  239. gd->ram_size = data->mem_dram_size;
  240. return 0;
  241. }
  242. U_BOOT_CMD(
  243. clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
  244. "display clocks",
  245. ""
  246. );