dram.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/armada100.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * ARMADA100 DRAM controller supports upto 8 banks
  15. * for chip select 0 and 1
  16. */
  17. /*
  18. * DDR Memory Control Registers
  19. * Refer Datasheet Appendix A.17
  20. */
  21. struct armd1ddr_map_registers {
  22. u32 cs; /* Memory Address Map Register -CS */
  23. u32 pad[3];
  24. };
  25. struct armd1ddr_registers {
  26. u8 pad[0x100 - 0x000];
  27. struct armd1ddr_map_registers mmap[2];
  28. };
  29. /*
  30. * armd1_sdram_base - reads SDRAM Base Address Register
  31. */
  32. u32 armd1_sdram_base(int chip_sel)
  33. {
  34. struct armd1ddr_registers *ddr_regs =
  35. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  36. u32 result = 0;
  37. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  38. if (!CS_valid)
  39. return 0;
  40. result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
  41. return result;
  42. }
  43. /*
  44. * armd1_sdram_size - reads SDRAM size
  45. */
  46. u32 armd1_sdram_size(int chip_sel)
  47. {
  48. struct armd1ddr_registers *ddr_regs =
  49. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  50. u32 result = 0;
  51. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  52. if (!CS_valid)
  53. return 0;
  54. result = readl(&ddr_regs->mmap[chip_sel].cs);
  55. result = (result >> 16) & 0xF;
  56. if (result < 0x7) {
  57. printf("Unknown DRAM Size\n");
  58. return -1;
  59. } else {
  60. return ((0x8 << (result - 0x7)) * 1024 * 1024);
  61. }
  62. }
  63. int dram_init(void)
  64. {
  65. int i;
  66. gd->ram_size = 0;
  67. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  68. gd->bd->bi_dram[i].start = armd1_sdram_base(i);
  69. gd->bd->bi_dram[i].size = armd1_sdram_size(i);
  70. /*
  71. * It is assumed that all memory banks are consecutive
  72. * and without gaps.
  73. * If the gap is found, ram_size will be reported for
  74. * consecutive memory only
  75. */
  76. if (gd->bd->bi_dram[i].start != gd->ram_size)
  77. break;
  78. gd->ram_size += gd->bd->bi_dram[i].size;
  79. }
  80. for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  81. /* If above loop terminated prematurely, we need to set
  82. * remaining banks' start address & size as 0. Otherwise other
  83. * u-boot functions and Linux kernel gets wrong values which
  84. * could result in crash */
  85. gd->bd->bi_dram[i].start = 0;
  86. gd->bd->bi_dram[i].size = 0;
  87. }
  88. return 0;
  89. }
  90. /*
  91. * If this function is not defined here,
  92. * board.c alters dram bank zero configuration defined above.
  93. */
  94. int dram_init_banksize(void)
  95. {
  96. dram_init();
  97. return 0;
  98. }