generic.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <init.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. static u32 mx31_decode_pll(u32 reg, u32 infreq)
  14. {
  15. u32 mfi = GET_PLL_MFI(reg);
  16. s32 mfn = GET_PLL_MFN(reg);
  17. u32 mfd = GET_PLL_MFD(reg);
  18. u32 pd = GET_PLL_PD(reg);
  19. mfi = mfi <= 5 ? 5 : mfi;
  20. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  21. mfd += 1;
  22. pd += 1;
  23. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  24. mfd * pd);
  25. }
  26. static u32 mx31_get_mpl_dpdgck_clk(void)
  27. {
  28. u32 infreq;
  29. if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
  30. infreq = MXC_CLK32 * 1024;
  31. else
  32. infreq = MXC_HCLK;
  33. return mx31_decode_pll(readl(CCM_MPCTL), infreq);
  34. }
  35. static u32 mx31_get_mcu_main_clk(void)
  36. {
  37. /* For now we assume mpl_dpdgck_clk == mcu_main_clk
  38. * which should be correct for most boards
  39. */
  40. return mx31_get_mpl_dpdgck_clk();
  41. }
  42. static u32 mx31_get_ipg_clk(void)
  43. {
  44. u32 freq = mx31_get_mcu_main_clk();
  45. u32 pdr0 = readl(CCM_PDR0);
  46. freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
  47. freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
  48. return freq;
  49. }
  50. /* hsp is the clock for the ipu */
  51. static u32 mx31_get_hsp_clk(void)
  52. {
  53. u32 freq = mx31_get_mcu_main_clk();
  54. u32 pdr0 = readl(CCM_PDR0);
  55. freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
  56. return freq;
  57. }
  58. void mx31_dump_clocks(void)
  59. {
  60. u32 cpufreq = mx31_get_mcu_main_clk();
  61. printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
  62. printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
  63. printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
  64. }
  65. unsigned int mxc_get_clock(enum mxc_clock clk)
  66. {
  67. switch (clk) {
  68. case MXC_ARM_CLK:
  69. return mx31_get_mcu_main_clk();
  70. case MXC_IPG_CLK:
  71. case MXC_IPG_PERCLK:
  72. case MXC_CSPI_CLK:
  73. case MXC_UART_CLK:
  74. case MXC_ESDHC_CLK:
  75. case MXC_I2C_CLK:
  76. return mx31_get_ipg_clk();
  77. case MXC_IPU_CLK:
  78. return mx31_get_hsp_clk();
  79. }
  80. return -1;
  81. }
  82. u32 imx_get_uartclk(void)
  83. {
  84. return mxc_get_clock(MXC_UART_CLK);
  85. }
  86. void mx31_gpio_mux(unsigned long mode)
  87. {
  88. unsigned long reg, shift, tmp;
  89. reg = IOMUXC_BASE + (mode & 0x1fc);
  90. shift = (~mode & 0x3) * 8;
  91. tmp = readl(reg);
  92. tmp &= ~(0xff << shift);
  93. tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
  94. writel(tmp, reg);
  95. }
  96. void mx31_set_pad(enum iomux_pins pin, u32 config)
  97. {
  98. u32 field, l, reg;
  99. pin &= IOMUX_PADNUM_MASK;
  100. reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
  101. field = (pin + 2) % 3;
  102. l = readl(reg);
  103. l &= ~(0x1ff << (field * 10));
  104. l |= config << (field * 10);
  105. writel(l, reg);
  106. }
  107. void mx31_set_gpr(enum iomux_gp_func gp, char en)
  108. {
  109. u32 l;
  110. struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
  111. l = readl(&iomuxc->gpr);
  112. if (en)
  113. l |= gp;
  114. else
  115. l &= ~gp;
  116. writel(l, &iomuxc->gpr);
  117. }
  118. void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
  119. {
  120. struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
  121. struct mx31_weim_cscr *cscr = &weim->cscr[cs];
  122. writel(weimcs->upper, &cscr->upper);
  123. writel(weimcs->lower, &cscr->lower);
  124. writel(weimcs->additional, &cscr->additional);
  125. }
  126. struct mx3_cpu_type mx31_cpu_type[] = {
  127. { .srev = 0x00, .v = 0x10 },
  128. { .srev = 0x10, .v = 0x11 },
  129. { .srev = 0x11, .v = 0x11 },
  130. { .srev = 0x12, .v = 0x1F },
  131. { .srev = 0x13, .v = 0x1F },
  132. { .srev = 0x14, .v = 0x12 },
  133. { .srev = 0x15, .v = 0x12 },
  134. { .srev = 0x28, .v = 0x20 },
  135. { .srev = 0x29, .v = 0x20 },
  136. };
  137. u32 get_cpu_rev(void)
  138. {
  139. u32 i, srev;
  140. /* read SREV register from IIM module */
  141. struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
  142. srev = readl(&iim->iim_srev);
  143. for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
  144. if (srev == mx31_cpu_type[i].srev)
  145. return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
  146. return srev | 0x8000;
  147. }
  148. static char *get_reset_cause(void)
  149. {
  150. /* read RCSR register from CCM module */
  151. struct clock_control_regs *ccm =
  152. (struct clock_control_regs *)CCM_BASE;
  153. u32 cause = readl(&ccm->rcsr) & 0x07;
  154. switch (cause) {
  155. case 0x0000:
  156. return "POR";
  157. case 0x0001:
  158. return "RST";
  159. case 0x0002:
  160. return "WDOG";
  161. case 0x0006:
  162. return "JTAG";
  163. case 0x0007:
  164. return "ARM11P power gating";
  165. default:
  166. return "unknown reset";
  167. }
  168. }
  169. #if defined(CONFIG_DISPLAY_CPUINFO)
  170. int print_cpuinfo(void)
  171. {
  172. u32 srev = get_cpu_rev();
  173. printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
  174. (srev & 0xF0) >> 4, (srev & 0x0F),
  175. ((srev & 0x8000) ? " unknown" : ""),
  176. mx31_get_mcu_main_clk() / 1000000);
  177. printf("Reset cause: %s\n", get_reset_cause());
  178. return 0;
  179. }
  180. #endif