phy.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. * Andy Fleming <afleming@gmail.com>
  5. *
  6. * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
  7. */
  8. #ifndef _PHY_H
  9. #define _PHY_H
  10. #include <linux/list.h>
  11. #include <linux/mii.h>
  12. #include <linux/ethtool.h>
  13. #include <linux/mdio.h>
  14. #define PHY_FIXED_ID 0xa5a55a5a
  15. #define PHY_MAX_ADDR 32
  16. #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
  17. #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
  18. SUPPORTED_TP | \
  19. SUPPORTED_MII)
  20. #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
  21. SUPPORTED_10baseT_Full)
  22. #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
  23. SUPPORTED_100baseT_Full)
  24. #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
  25. SUPPORTED_1000baseT_Full)
  26. #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
  27. PHY_100BT_FEATURES | \
  28. PHY_DEFAULT_FEATURES)
  29. #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
  30. PHY_1000BT_FEATURES)
  31. #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
  32. SUPPORTED_10000baseT_Full)
  33. #ifndef PHY_ANEG_TIMEOUT
  34. #define PHY_ANEG_TIMEOUT 4000
  35. #endif
  36. typedef enum {
  37. PHY_INTERFACE_MODE_MII,
  38. PHY_INTERFACE_MODE_GMII,
  39. PHY_INTERFACE_MODE_SGMII,
  40. PHY_INTERFACE_MODE_SGMII_2500,
  41. PHY_INTERFACE_MODE_QSGMII,
  42. PHY_INTERFACE_MODE_TBI,
  43. PHY_INTERFACE_MODE_RMII,
  44. PHY_INTERFACE_MODE_RGMII,
  45. PHY_INTERFACE_MODE_RGMII_ID,
  46. PHY_INTERFACE_MODE_RGMII_RXID,
  47. PHY_INTERFACE_MODE_RGMII_TXID,
  48. PHY_INTERFACE_MODE_RTBI,
  49. PHY_INTERFACE_MODE_XGMII,
  50. PHY_INTERFACE_MODE_XAUI,
  51. PHY_INTERFACE_MODE_RXAUI,
  52. PHY_INTERFACE_MODE_SFI,
  53. PHY_INTERFACE_MODE_NONE, /* Must be last */
  54. PHY_INTERFACE_MODE_COUNT,
  55. } phy_interface_t;
  56. static const char *phy_interface_strings[] = {
  57. [PHY_INTERFACE_MODE_MII] = "mii",
  58. [PHY_INTERFACE_MODE_GMII] = "gmii",
  59. [PHY_INTERFACE_MODE_SGMII] = "sgmii",
  60. [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
  61. [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
  62. [PHY_INTERFACE_MODE_TBI] = "tbi",
  63. [PHY_INTERFACE_MODE_RMII] = "rmii",
  64. [PHY_INTERFACE_MODE_RGMII] = "rgmii",
  65. [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
  66. [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
  67. [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
  68. [PHY_INTERFACE_MODE_RTBI] = "rtbi",
  69. [PHY_INTERFACE_MODE_XGMII] = "xgmii",
  70. [PHY_INTERFACE_MODE_XAUI] = "xaui",
  71. [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
  72. [PHY_INTERFACE_MODE_SFI] = "sfi",
  73. [PHY_INTERFACE_MODE_NONE] = "",
  74. };
  75. static inline const char *phy_string_for_interface(phy_interface_t i)
  76. {
  77. /* Default to unknown */
  78. if (i > PHY_INTERFACE_MODE_NONE)
  79. i = PHY_INTERFACE_MODE_NONE;
  80. return phy_interface_strings[i];
  81. }
  82. struct phy_device;
  83. #define MDIO_NAME_LEN 32
  84. struct mii_dev {
  85. struct list_head link;
  86. char name[MDIO_NAME_LEN];
  87. void *priv;
  88. int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
  89. int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
  90. u16 val);
  91. int (*reset)(struct mii_dev *bus);
  92. struct phy_device *phymap[PHY_MAX_ADDR];
  93. u32 phy_mask;
  94. };
  95. /* struct phy_driver: a structure which defines PHY behavior
  96. *
  97. * uid will contain a number which represents the PHY. During
  98. * startup, the driver will poll the PHY to find out what its
  99. * UID--as defined by registers 2 and 3--is. The 32-bit result
  100. * gotten from the PHY will be masked to
  101. * discard any bits which may change based on revision numbers
  102. * unimportant to functionality
  103. *
  104. */
  105. struct phy_driver {
  106. char *name;
  107. unsigned int uid;
  108. unsigned int mask;
  109. unsigned int mmds;
  110. u32 features;
  111. /* Called to do any driver startup necessities */
  112. /* Will be called during phy_connect */
  113. int (*probe)(struct phy_device *phydev);
  114. /* Called to configure the PHY, and modify the controller
  115. * based on the results. Should be called after phy_connect */
  116. int (*config)(struct phy_device *phydev);
  117. /* Called when starting up the controller */
  118. int (*startup)(struct phy_device *phydev);
  119. /* Called when bringing down the controller */
  120. int (*shutdown)(struct phy_device *phydev);
  121. int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
  122. int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
  123. u16 val);
  124. struct list_head list;
  125. };
  126. struct phy_device {
  127. /* Information about the PHY type */
  128. /* And management functions */
  129. struct mii_dev *bus;
  130. struct phy_driver *drv;
  131. void *priv;
  132. #ifdef CONFIG_DM_ETH
  133. struct udevice *dev;
  134. #else
  135. struct eth_device *dev;
  136. #endif
  137. /* forced speed & duplex (no autoneg)
  138. * partner speed & duplex & pause (autoneg)
  139. */
  140. int speed;
  141. int duplex;
  142. /* The most recently read link state */
  143. int link;
  144. int port;
  145. phy_interface_t interface;
  146. u32 advertising;
  147. u32 supported;
  148. u32 mmds;
  149. int autoneg;
  150. int addr;
  151. int pause;
  152. int asym_pause;
  153. u32 phy_id;
  154. u32 flags;
  155. };
  156. struct fixed_link {
  157. int phy_id;
  158. int duplex;
  159. int link_speed;
  160. int pause;
  161. int asym_pause;
  162. };
  163. static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
  164. {
  165. struct mii_dev *bus = phydev->bus;
  166. return bus->read(bus, phydev->addr, devad, regnum);
  167. }
  168. static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
  169. u16 val)
  170. {
  171. struct mii_dev *bus = phydev->bus;
  172. return bus->write(bus, phydev->addr, devad, regnum, val);
  173. }
  174. #ifdef CONFIG_PHYLIB_10G
  175. extern struct phy_driver gen10g_driver;
  176. /* For now, XGMII is the only 10G interface */
  177. static inline int is_10g_interface(phy_interface_t interface)
  178. {
  179. return interface == PHY_INTERFACE_MODE_XGMII;
  180. }
  181. #endif
  182. int phy_init(void);
  183. int phy_reset(struct phy_device *phydev);
  184. struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
  185. phy_interface_t interface);
  186. #ifdef CONFIG_DM_ETH
  187. void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
  188. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  189. struct udevice *dev,
  190. phy_interface_t interface);
  191. #else
  192. void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
  193. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  194. struct eth_device *dev,
  195. phy_interface_t interface);
  196. #endif
  197. int phy_startup(struct phy_device *phydev);
  198. int phy_config(struct phy_device *phydev);
  199. int phy_shutdown(struct phy_device *phydev);
  200. int phy_register(struct phy_driver *drv);
  201. int phy_set_supported(struct phy_device *phydev, u32 max_speed);
  202. int genphy_config_aneg(struct phy_device *phydev);
  203. int genphy_restart_aneg(struct phy_device *phydev);
  204. int genphy_update_link(struct phy_device *phydev);
  205. int genphy_parse_link(struct phy_device *phydev);
  206. int genphy_config(struct phy_device *phydev);
  207. int genphy_startup(struct phy_device *phydev);
  208. int genphy_shutdown(struct phy_device *phydev);
  209. int gen10g_config(struct phy_device *phydev);
  210. int gen10g_startup(struct phy_device *phydev);
  211. int gen10g_shutdown(struct phy_device *phydev);
  212. int gen10g_discover_mmds(struct phy_device *phydev);
  213. int phy_b53_init(void);
  214. int phy_mv88e61xx_init(void);
  215. int phy_aquantia_init(void);
  216. int phy_atheros_init(void);
  217. int phy_broadcom_init(void);
  218. int phy_cortina_init(void);
  219. int phy_davicom_init(void);
  220. int phy_et1011c_init(void);
  221. int phy_lxt_init(void);
  222. int phy_marvell_init(void);
  223. int phy_micrel_ksz8xxx_init(void);
  224. int phy_micrel_ksz90x1_init(void);
  225. int phy_meson_gxl_init(void);
  226. int phy_natsemi_init(void);
  227. int phy_realtek_init(void);
  228. int phy_smsc_init(void);
  229. int phy_teranetics_init(void);
  230. int phy_ti_init(void);
  231. int phy_vitesse_init(void);
  232. int phy_xilinx_init(void);
  233. int phy_mscc_init(void);
  234. int phy_fixed_init(void);
  235. int board_phy_config(struct phy_device *phydev);
  236. int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
  237. /**
  238. * phy_get_interface_by_name() - Look up a PHY interface name
  239. *
  240. * @str: PHY interface name, e.g. "mii"
  241. * @return PHY_INTERFACE_MODE_... value, or -1 if not found
  242. */
  243. int phy_get_interface_by_name(const char *str);
  244. /**
  245. * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
  246. * is RGMII (all variants)
  247. * @phydev: the phy_device struct
  248. */
  249. static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
  250. {
  251. return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
  252. phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
  253. }
  254. /**
  255. * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
  256. * is SGMII (all variants)
  257. * @phydev: the phy_device struct
  258. */
  259. static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
  260. {
  261. return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
  262. phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
  263. }
  264. /* PHY UIDs for various PHYs that are referenced in external code */
  265. #define PHY_UID_CS4340 0x13e51002
  266. #define PHY_UID_TN2020 0x00a19410
  267. #endif