atf_common.h 6.5 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * This is from the ARM TF Project,
  4. * Repository: https://github.com/ARM-software/arm-trusted-firmware.git
  5. * File: include/common/bl_common.h
  6. * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
  7. * reserved.
  8. * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
  9. */
  10. #ifndef __BL_COMMON_H__
  11. #define __BL_COMMON_H__
  12. #define ATF_PARAM_EP 0x01
  13. #define ATF_PARAM_IMAGE_BINARY 0x02
  14. #define ATF_PARAM_BL31 0x03
  15. #define ATF_PARAM_BL_PARAMS 0x05
  16. #define ATF_VERSION_1 0x01
  17. #define ATF_VERSION_2 0x02
  18. #define ATF_BL31_IMAGE_ID 0x03
  19. #define ATF_BL32_IMAGE_ID 0x04
  20. #define ATF_BL33_IMAGE_ID 0x05
  21. #define ATF_EP_SECURE 0x0
  22. #define ATF_EP_NON_SECURE 0x1
  23. #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
  24. (_p)->h.type = (uint8_t)(_type); \
  25. (_p)->h.version = (uint8_t)(_ver); \
  26. (_p)->h.size = (uint16_t)sizeof(*_p); \
  27. (_p)->h.attr = (uint32_t)(_attr) ; \
  28. } while (0)
  29. #define MODE_RW_SHIFT 0x4
  30. #define MODE_RW_MASK 0x1
  31. #define MODE_RW_64 0x0
  32. #define MODE_RW_32 0x1
  33. #define MODE_EL_SHIFT 0x2
  34. #define MODE_EL_MASK 0x3
  35. #define MODE_EL3 0x3
  36. #define MODE_EL2 0x2
  37. #define MODE_EL1 0x1
  38. #define MODE_EL0 0x0
  39. #define MODE_SP_SHIFT 0x0
  40. #define MODE_SP_MASK 0x1
  41. #define MODE_SP_EL0 0x0
  42. #define MODE_SP_ELX 0x1
  43. #define SPSR_DAIF_SHIFT 6
  44. #define SPSR_DAIF_MASK 0x0f
  45. #define SPSR_64(el, sp, daif) \
  46. (MODE_RW_64 << MODE_RW_SHIFT | \
  47. ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
  48. ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
  49. ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
  50. #define SPSR_FIQ (1 << 6)
  51. #define SPSR_IRQ (1 << 7)
  52. #define SPSR_SERROR (1 << 8)
  53. #define SPSR_DEBUG (1 << 9)
  54. #define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
  55. #define DAIF_FIQ_BIT (1<<0)
  56. #define DAIF_IRQ_BIT (1<<1)
  57. #define DAIF_ABT_BIT (1<<2)
  58. #define DAIF_DBG_BIT (1<<3)
  59. #define DISABLE_ALL_EXECPTIONS \
  60. (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
  61. #ifndef __ASSEMBLY__
  62. /*******************************************************************************
  63. * Structure used for telling the next BL how much of a particular type of
  64. * memory is available for its use and how much is already used.
  65. ******************************************************************************/
  66. struct aapcs64_params {
  67. unsigned long arg0;
  68. unsigned long arg1;
  69. unsigned long arg2;
  70. unsigned long arg3;
  71. unsigned long arg4;
  72. unsigned long arg5;
  73. unsigned long arg6;
  74. unsigned long arg7;
  75. };
  76. /***************************************************************************
  77. * This structure provides version information and the size of the
  78. * structure, attributes for the structure it represents
  79. ***************************************************************************/
  80. struct param_header {
  81. uint8_t type; /* type of the structure */
  82. uint8_t version; /* version of this structure */
  83. uint16_t size; /* size of this structure in bytes */
  84. uint32_t attr; /* attributes: unused bits SBZ */
  85. };
  86. /*****************************************************************************
  87. * This structure represents the superset of information needed while
  88. * switching exception levels. The only two mechanisms to do so are
  89. * ERET & SMC. Security state is indicated using bit zero of header
  90. * attribute
  91. * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
  92. * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
  93. * processing SMC to jump to BL31.
  94. *****************************************************************************/
  95. struct entry_point_info {
  96. struct param_header h;
  97. uintptr_t pc;
  98. uint32_t spsr;
  99. struct aapcs64_params args;
  100. };
  101. /*****************************************************************************
  102. * Image info binary provides information from the image loader that
  103. * can be used by the firmware to manage available trusted RAM.
  104. * More advanced firmware image formats can provide additional
  105. * information that enables optimization or greater flexibility in the
  106. * common firmware code
  107. *****************************************************************************/
  108. struct atf_image_info {
  109. struct param_header h;
  110. uintptr_t image_base; /* physical address of base of image */
  111. uint32_t image_size; /* bytes read from image file */
  112. #if CONFIG_IS_ENABLED(ATF_LOAD_IMAGE_V2)
  113. uint32_t image_max_size;
  114. #endif
  115. };
  116. /*****************************************************************************
  117. * The image descriptor struct definition.
  118. *****************************************************************************/
  119. struct image_desc {
  120. /* Contains unique image id for the image. */
  121. unsigned int image_id;
  122. /*
  123. * This member contains Image state information.
  124. * Refer IMAGE_STATE_XXX defined above.
  125. */
  126. unsigned int state;
  127. uint32_t copied_size; /* image size copied in blocks */
  128. struct atf_image_info atf_image_info;
  129. struct entry_point_info ep_info;
  130. };
  131. /*******************************************************************************
  132. * This structure represents the superset of information that can be passed to
  133. * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
  134. * populated only if BL2 detects its presence. A pointer to a structure of this
  135. * type should be passed in X0 to BL31's cold boot entrypoint.
  136. *
  137. * Use of this structure and the X0 parameter is not mandatory: the BL31
  138. * platform code can use other mechanisms to provide the necessary information
  139. * about BL32 and BL33 to the common and SPD code.
  140. *
  141. * BL31 image information is mandatory if this structure is used. If either of
  142. * the optional BL32 and BL33 image information is not provided, this is
  143. * indicated by the respective image_info pointers being zero.
  144. ******************************************************************************/
  145. struct bl31_params {
  146. struct param_header h;
  147. struct atf_image_info *bl31_image_info;
  148. struct entry_point_info *bl32_ep_info;
  149. struct atf_image_info *bl32_image_info;
  150. struct entry_point_info *bl33_ep_info;
  151. struct atf_image_info *bl33_image_info;
  152. };
  153. /* BL image node in the BL image execution sequence */
  154. struct bl_params_node {
  155. unsigned int image_id;
  156. struct atf_image_info *image_info;
  157. struct entry_point_info *ep_info;
  158. struct bl_params_node *next_params_info;
  159. };
  160. /*
  161. * BL image head node in the BL image execution sequence
  162. * It is also used to pass information to next BL image.
  163. */
  164. struct bl_params {
  165. struct param_header h;
  166. struct bl_params_node *head;
  167. };
  168. #define for_each_bl_params_node(bl_params, node) \
  169. for ((node) = (bl_params)->head; \
  170. (node); \
  171. (node) = (node)->next_params_info)
  172. #endif /*__ASSEMBLY__ */
  173. #endif /* __BL_COMMON_H__ */