ftssp010_spi.c 12 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
  4. * Kuo-Jung Su <dantesu@gmail.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <linux/compat.h>
  10. #include <asm/io.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #ifndef CONFIG_FTSSP010_BASE_LIST
  14. #define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
  15. #endif
  16. #ifndef CONFIG_FTSSP010_GPIO_BASE
  17. #define CONFIG_FTSSP010_GPIO_BASE 0
  18. #endif
  19. #ifndef CONFIG_FTSSP010_GPIO_LIST
  20. #define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
  21. #endif
  22. #ifndef CONFIG_FTSSP010_CLOCK
  23. #define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
  24. #endif
  25. #ifndef CONFIG_FTSSP010_TIMEOUT
  26. #define CONFIG_FTSSP010_TIMEOUT 100
  27. #endif
  28. /* FTSSP010 chip registers */
  29. struct ftssp010_regs {
  30. uint32_t cr[3];/* control register */
  31. uint32_t sr; /* status register */
  32. uint32_t icr; /* interrupt control register */
  33. uint32_t isr; /* interrupt status register */
  34. uint32_t dr; /* data register */
  35. uint32_t rsvd[17];
  36. uint32_t revr; /* revision register */
  37. uint32_t fear; /* feature register */
  38. };
  39. /* Control Register 0 */
  40. #define CR0_FFMT_MASK (7 << 12)
  41. #define CR0_FFMT_SSP (0 << 12)
  42. #define CR0_FFMT_SPI (1 << 12)
  43. #define CR0_FFMT_MICROWIRE (2 << 12)
  44. #define CR0_FFMT_I2S (3 << 12)
  45. #define CR0_FFMT_AC97 (4 << 12)
  46. #define CR0_FLASH (1 << 11)
  47. #define CR0_FSDIST(x) (((x) & 0x03) << 8)
  48. #define CR0_LOOP (1 << 7) /* loopback mode */
  49. #define CR0_LSB (1 << 6) /* LSB */
  50. #define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
  51. #define CR0_FSJUSTIFY (1 << 4)
  52. #define CR0_OPM_SLAVE (0 << 2)
  53. #define CR0_OPM_MASTER (3 << 2)
  54. #define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
  55. #define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
  56. #define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
  57. #define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
  58. #define CR0_SCLKPO (1 << 1) /* clock polarity */
  59. #define CR0_SCLKPH (1 << 0) /* clock phase */
  60. /* Control Register 1 */
  61. #define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
  62. #define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
  63. #define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
  64. /* Control Register 2 */
  65. #define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
  66. #define CR2_FS (1 << 9) /* CS/FS signal level */
  67. #define CR2_TXEN (1 << 8) /* tx enable */
  68. #define CR2_RXEN (1 << 7) /* rx enable */
  69. #define CR2_RESET (1 << 6) /* chip reset */
  70. #define CR2_TXFC (1 << 3) /* tx fifo Clear */
  71. #define CR2_RXFC (1 << 2) /* rx fifo Clear */
  72. #define CR2_TXDOE (1 << 1) /* tx data output enable */
  73. #define CR2_EN (1 << 0) /* chip enable */
  74. /* Status Register */
  75. #define SR_RFF (1 << 0) /* rx fifo full */
  76. #define SR_TFNF (1 << 1) /* tx fifo not full */
  77. #define SR_BUSY (1 << 2) /* chip busy */
  78. #define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
  79. #define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
  80. /* Feature Register */
  81. #define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
  82. #define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
  83. #define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
  84. #define FEAR_AC97 (1 << 24)
  85. #define FEAR_I2S (1 << 25)
  86. #define FEAR_SPI_MWR (1 << 26)
  87. #define FEAR_SSP (1 << 27)
  88. #define FEAR_SPDIF (1 << 28)
  89. /* FTGPIO010 chip registers */
  90. struct ftgpio010_regs {
  91. uint32_t out; /* 0x00: Data Output */
  92. uint32_t in; /* 0x04: Data Input */
  93. uint32_t dir; /* 0x08: Direction */
  94. uint32_t bypass; /* 0x0c: Bypass */
  95. uint32_t set; /* 0x10: Data Set */
  96. uint32_t clr; /* 0x14: Data Clear */
  97. uint32_t pull_up; /* 0x18: Pull-Up Enabled */
  98. uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
  99. };
  100. struct ftssp010_gpio {
  101. struct ftgpio010_regs *regs;
  102. uint32_t pin;
  103. };
  104. struct ftssp010_spi {
  105. struct spi_slave slave;
  106. struct ftssp010_gpio gpio;
  107. struct ftssp010_regs *regs;
  108. uint32_t fifo;
  109. uint32_t mode;
  110. uint32_t div;
  111. uint32_t clk;
  112. uint32_t speed;
  113. uint32_t revision;
  114. };
  115. static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
  116. {
  117. return container_of(slave, struct ftssp010_spi, slave);
  118. }
  119. static int get_spi_chip(int bus, struct ftssp010_spi *chip)
  120. {
  121. uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
  122. if (bus >= ARRAY_SIZE(base) || !base[bus])
  123. return -1;
  124. chip->regs = (struct ftssp010_regs *)base[bus];
  125. chip->revision = readl(&chip->regs->revr);
  126. fear = readl(&chip->regs->fear);
  127. chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
  128. return 0;
  129. }
  130. static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
  131. {
  132. uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
  133. if (bus >= ARRAY_SIZE(base) || !base[bus])
  134. return -1;
  135. chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
  136. chip->pin = base[bus] & 0x1f;
  137. /* make it an output pin */
  138. setbits_le32(&chip->regs->dir, 1 << chip->pin);
  139. return 0;
  140. }
  141. static int ftssp010_wait(struct ftssp010_spi *chip)
  142. {
  143. struct ftssp010_regs *regs = chip->regs;
  144. int ret = -1;
  145. ulong t;
  146. /* wait until device idle */
  147. for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
  148. if (readl(&regs->sr) & SR_BUSY)
  149. continue;
  150. ret = 0;
  151. break;
  152. }
  153. if (ret)
  154. puts("ftspi010: busy timeout\n");
  155. return ret;
  156. }
  157. static int ftssp010_wait_tx(struct ftssp010_spi *chip)
  158. {
  159. struct ftssp010_regs *regs = chip->regs;
  160. int ret = -1;
  161. ulong t;
  162. /* wait until tx fifo not full */
  163. for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
  164. if (!(readl(&regs->sr) & SR_TFNF))
  165. continue;
  166. ret = 0;
  167. break;
  168. }
  169. if (ret)
  170. puts("ftssp010: tx timeout\n");
  171. return ret;
  172. }
  173. static int ftssp010_wait_rx(struct ftssp010_spi *chip)
  174. {
  175. struct ftssp010_regs *regs = chip->regs;
  176. int ret = -1;
  177. ulong t;
  178. /* wait until rx fifo not empty */
  179. for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
  180. if (!SR_RFVE(readl(&regs->sr)))
  181. continue;
  182. ret = 0;
  183. break;
  184. }
  185. if (ret)
  186. puts("ftssp010: rx timeout\n");
  187. return ret;
  188. }
  189. static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
  190. const void *tx_buf, void *rx_buf, int len, uint flags)
  191. {
  192. struct ftssp010_regs *regs = chip->regs;
  193. const uint8_t *txb = tx_buf;
  194. uint8_t *rxb = rx_buf;
  195. while (len > 0) {
  196. int i, depth = min(chip->fifo >> 2, len);
  197. uint32_t xmsk = 0;
  198. if (tx_buf) {
  199. for (i = 0; i < depth; ++i) {
  200. ftssp010_wait_tx(chip);
  201. writel(*txb++, &regs->dr);
  202. }
  203. xmsk |= CR2_TXEN | CR2_TXDOE;
  204. if ((readl(&regs->cr[2]) & xmsk) != xmsk)
  205. setbits_le32(&regs->cr[2], xmsk);
  206. }
  207. if (rx_buf) {
  208. xmsk |= CR2_RXEN;
  209. if ((readl(&regs->cr[2]) & xmsk) != xmsk)
  210. setbits_le32(&regs->cr[2], xmsk);
  211. for (i = 0; i < depth; ++i) {
  212. ftssp010_wait_rx(chip);
  213. *rxb++ = (uint8_t)readl(&regs->dr);
  214. }
  215. }
  216. len -= depth;
  217. }
  218. return 0;
  219. }
  220. static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
  221. const void *tx_buf, void *rx_buf, int len, uint flags)
  222. {
  223. struct ftssp010_regs *regs = chip->regs;
  224. const uint8_t *txb = tx_buf;
  225. uint8_t *rxb = rx_buf;
  226. while (len > 0) {
  227. int i, depth = min(chip->fifo >> 2, len);
  228. uint32_t tmp;
  229. for (i = 0; i < depth; ++i) {
  230. ftssp010_wait_tx(chip);
  231. writel(txb ? (*txb++) : 0, &regs->dr);
  232. }
  233. for (i = 0; i < depth; ++i) {
  234. ftssp010_wait_rx(chip);
  235. tmp = readl(&regs->dr);
  236. if (rxb)
  237. *rxb++ = (uint8_t)tmp;
  238. }
  239. len -= depth;
  240. }
  241. return 0;
  242. }
  243. static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
  244. {
  245. struct ftssp010_regs *regs = chip->regs;
  246. struct ftssp010_gpio *gpio = &chip->gpio;
  247. uint32_t mask;
  248. /* cs pull high/low */
  249. if (chip->revision >= 0x11900) {
  250. mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
  251. writel(mask, &regs->cr[2]);
  252. } else if (gpio->regs) {
  253. mask = 1 << gpio->pin;
  254. if (high)
  255. writel(mask, &gpio->regs->set);
  256. else
  257. writel(mask, &gpio->regs->clr);
  258. }
  259. /* extra delay for signal propagation */
  260. udelay_masked(1);
  261. }
  262. /*
  263. * Determine if a SPI chipselect is valid.
  264. * This function is provided by the board if the low-level SPI driver
  265. * needs it to determine if a given chipselect is actually valid.
  266. *
  267. * Returns: 1 if bus:cs identifies a valid chip on this board, 0
  268. * otherwise.
  269. */
  270. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  271. {
  272. struct ftssp010_spi chip;
  273. if (get_spi_chip(bus, &chip))
  274. return 0;
  275. if (!cs)
  276. return 1;
  277. else if ((cs < 4) && (chip.revision >= 0x11900))
  278. return 1;
  279. return 0;
  280. }
  281. /*
  282. * Activate a SPI chipselect.
  283. * This function is provided by the board code when using a driver
  284. * that can't control its chipselects automatically (e.g.
  285. * common/soft_spi.c). When called, it should activate the chip select
  286. * to the device identified by "slave".
  287. */
  288. void spi_cs_activate(struct spi_slave *slave)
  289. {
  290. struct ftssp010_spi *chip = to_ftssp010_spi(slave);
  291. struct ftssp010_regs *regs = chip->regs;
  292. /* cs pull */
  293. if (chip->mode & SPI_CS_HIGH)
  294. ftssp010_cs_set(chip, 1);
  295. else
  296. ftssp010_cs_set(chip, 0);
  297. /* chip enable + fifo clear */
  298. setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
  299. }
  300. /*
  301. * Deactivate a SPI chipselect.
  302. * This function is provided by the board code when using a driver
  303. * that can't control its chipselects automatically (e.g.
  304. * common/soft_spi.c). When called, it should deactivate the chip
  305. * select to the device identified by "slave".
  306. */
  307. void spi_cs_deactivate(struct spi_slave *slave)
  308. {
  309. struct ftssp010_spi *chip = to_ftssp010_spi(slave);
  310. /* wait until chip idle */
  311. ftssp010_wait(chip);
  312. /* cs pull */
  313. if (chip->mode & SPI_CS_HIGH)
  314. ftssp010_cs_set(chip, 0);
  315. else
  316. ftssp010_cs_set(chip, 1);
  317. }
  318. void spi_init(void)
  319. {
  320. /* nothing to do */
  321. }
  322. struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
  323. {
  324. struct ftssp010_spi *chip;
  325. if (mode & SPI_3WIRE) {
  326. puts("ftssp010: can't do 3-wire\n");
  327. return NULL;
  328. }
  329. if (mode & SPI_SLAVE) {
  330. puts("ftssp010: can't do slave mode\n");
  331. return NULL;
  332. }
  333. if (mode & SPI_PREAMBLE) {
  334. puts("ftssp010: can't skip preamble bytes\n");
  335. return NULL;
  336. }
  337. if (!spi_cs_is_valid(bus, cs)) {
  338. puts("ftssp010: invalid (bus, cs)\n");
  339. return NULL;
  340. }
  341. chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
  342. if (!chip)
  343. return NULL;
  344. if (get_spi_chip(bus, chip))
  345. goto free_out;
  346. if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
  347. puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
  348. "controlled by tx engine which is not synced with rx engine,\n"
  349. "so the clock & cs might be shutdown before rx engine\n"
  350. "finishs its jobs.\n"
  351. "If possible, please add a dedicated gpio for it.\n");
  352. }
  353. chip->mode = mode;
  354. chip->clk = CONFIG_FTSSP010_CLOCK;
  355. chip->div = 2;
  356. if (max_hz) {
  357. while (chip->div < 0xffff) {
  358. if ((chip->clk / (2 * chip->div)) <= max_hz)
  359. break;
  360. chip->div += 1;
  361. }
  362. }
  363. chip->speed = chip->clk / (2 * chip->div);
  364. return &chip->slave;
  365. free_out:
  366. free(chip);
  367. return NULL;
  368. }
  369. void spi_free_slave(struct spi_slave *slave)
  370. {
  371. free(slave);
  372. }
  373. int spi_claim_bus(struct spi_slave *slave)
  374. {
  375. struct ftssp010_spi *chip = to_ftssp010_spi(slave);
  376. struct ftssp010_regs *regs = chip->regs;
  377. writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]);
  378. if (chip->revision >= 0x11900) {
  379. writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
  380. &regs->cr[0]);
  381. writel(CR2_TXFC | CR2_RXFC,
  382. &regs->cr[2]);
  383. } else {
  384. writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
  385. &regs->cr[0]);
  386. writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
  387. &regs->cr[2]);
  388. }
  389. if (chip->mode & SPI_LOOP)
  390. setbits_le32(&regs->cr[0], CR0_LOOP);
  391. if (chip->mode & SPI_CPOL)
  392. setbits_le32(&regs->cr[0], CR0_SCLKPO);
  393. if (chip->mode & SPI_CPHA)
  394. setbits_le32(&regs->cr[0], CR0_SCLKPH);
  395. spi_cs_deactivate(slave);
  396. return 0;
  397. }
  398. void spi_release_bus(struct spi_slave *slave)
  399. {
  400. struct ftssp010_spi *chip = to_ftssp010_spi(slave);
  401. struct ftssp010_regs *regs = chip->regs;
  402. writel(0, &regs->cr[2]);
  403. }
  404. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  405. const void *dout, void *din, unsigned long flags)
  406. {
  407. struct ftssp010_spi *chip = to_ftssp010_spi(slave);
  408. uint32_t len = bitlen >> 3;
  409. if (flags & SPI_XFER_BEGIN)
  410. spi_cs_activate(slave);
  411. if (chip->revision >= 0x11900)
  412. ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
  413. else
  414. ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
  415. if (flags & SPI_XFER_END)
  416. spi_cs_deactivate(slave);
  417. return 0;
  418. }