b4860qds.rst 15 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. B4860QDS
  3. ========
  4. The B4860QDS is a Freescale reference board that hosts the B4860 SoC
  5. (and variants).
  6. B4860 Overview
  7. --------------
  8. The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
  9. StarCore and Power Architecture® cores. It targets the broadband wireless
  10. infrastructure and builds upon the proven success of the existing multicore
  11. DSPs and Power CPUs. It is designed to bolster the rapidly changing and
  12. expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
  13. The B4860 is a highly-integrated StarCore and Power Architecture processor that
  14. contains:
  15. * Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
  16. clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
  17. for wireless base station applications
  18. * Four dual-thread e6500 Power Architecture processors organized in one
  19. cluster-each core runs up to 1.8 GHz
  20. * Two DDR3/3L controllers for high-speed, industry-standard memory interface
  21. each runs at up to 1866.67 MHz
  22. * MAPLE-B3 hardware acceleration-for forward error correction schemes including
  23. Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
  24. equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
  25. FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
  26. acceleration
  27. * CoreNet fabric that fully supports coherency using MESI protocol between the
  28. e6500 cores, SC3900 FVP cores, memories and external interfaces.
  29. CoreNet fabric interconnect runs at 667 MHz and supports coherent and
  30. non-coherent out of order transactions with prioritization and bandwidth
  31. allocation amongst CoreNet endpoints.
  32. * Data Path Acceleration Architecture, which includes the following:
  33. * Frame Manager (FMan), which supports in-line packet parsing and general
  34. classification to enable policing and QoS-based packet distribution
  35. * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
  36. of queue management, task management, load distribution, flow ordering,
  37. buffer management, and allocation tasks from the cores
  38. * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
  39. IPsec, SSL, and 802.16
  40. * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
  41. and outbound). Supports types 5, 6 (outbound only)
  42. * Large internal cache memory with snooping and stashing capabilities for
  43. bandwidth saving and high utilization of processor elements. The 9856-Kbyte
  44. internal memory space includes the following:
  45. * 32 Kbyte L1 ICache per e6500/SC3900 core
  46. * 32 Kbyte L1 DCache per e6500/SC3900 core
  47. * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  48. * 2048 Kbyte unified L2 cache for the e6500 cluster
  49. * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
  50. * Sixteen 10-GHz SerDes lanes serving:
  51. * Two Serial RapidIO interfaces
  52. * Each supports up to 4 lanes and a total of up to 8 lanes
  53. * Up to 8-lanes Common Public Radio Interface (CPRI) controller for
  54. glue-less antenna connection
  55. * Two 10-Gbit Ethernet controllers (10GEC)
  56. * Six 1G/2.5-Gbit Ethernet controllers for network communications
  57. * PCI Express controller
  58. * Debug (Aurora)
  59. * Two OCeaN DMAs
  60. * Various system peripherals
  61. * 182 32-bit timers
  62. B4860QDS Overview
  63. -----------------
  64. - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  65. ECC, 4 GB of memory in two ranks of 2 GB.
  66. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  67. ECC, 2 GB of memory. Single rank.
  68. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  69. 16x16 switch VSC3316
  70. - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  71. 8x8 switch VSC3308
  72. - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
  73. B4860 UART port is available over USB-to-UART translator USB2SER or over
  74. RS232 flat cable.
  75. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
  76. copper connectors for Stand-alone mode and to the 1000Base-X over AMC
  77. MicroTCA connector ports 0 and 2 for AMC mode.
  78. - The B4860 configuration may be loaded from nine bits coded reset configuration
  79. reset source. The RCW source is set by appropriate DIP-switches.
  80. - 16-bit NOR Flash / PROMJet
  81. - QIXIS 8-bit NOR Flash Emulator
  82. - 8-bit NAND Flash
  83. - 24-bit SPI Flash
  84. - Long address I2C EEPROM
  85. - Available debug interfaces are:
  86. - On-board eCWTAP controller with ETH and USB I/F
  87. - JTAG/COP 16-pin header for any external TAP controller
  88. - External JTAG source over AMC to support B2B configuration
  89. - 70-pin Aurora debug connector
  90. - QIXIS (FPGA) logic:
  91. - 2 KB internal memory space including
  92. - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  93. DDRCLK1,2 and RTCCLK.
  94. - Two 8T49N222A SerDes ref clock devices support two SerDes port clock
  95. frequency - total four refclk, including CPRI clock scheme.
  96. B4420 Personality
  97. -----------------
  98. B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
  99. and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
  100. and reduced target frequencies.
  101. Key differences between B4860 and B4420
  102. ---------------------------------------
  103. B4420 has:
  104. 1. Less e6500 cores: 1 cluster with 2 e6500 cores
  105. 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
  106. 3. Single DDRC
  107. 4. 2X 4 lane serdes
  108. 5. 3 SGMII interfaces
  109. 6. no sRIO
  110. 7. no 10G
  111. B4860QDS Default Settings
  112. -------------------------
  113. Switch Settings
  114. ^^^^^^^^^^^^^^^
  115. .. code-block:: none
  116. SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
  117. SW2 ON ON ON ON ON ON OFF OFF
  118. SW3 OFF OFF OFF ON OFF OFF ON OFF
  119. SW5 OFF OFF OFF OFF OFF OFF ON ON
  120. Note:
  121. - PCIe slots modes: All the PCIe devices work as Root Complex.
  122. - Boot location: NOR flash.
  123. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
  124. 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
  125. NAND boot::
  126. SW1 [1.1] = 0
  127. SW2 [1.1] = 1
  128. SW3 [1:4] = 0001
  129. NOR boot::
  130. SW1 [1.1] = 1
  131. SW2 [1.1] = 0
  132. SW3 [1:4] = 1000
  133. B4420QDS Default Settings
  134. -------------------------
  135. Switch Settings
  136. ^^^^^^^^^^^^^^^
  137. .. code-block:: none
  138. SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
  139. SW2 ON OFF ON OFF ON ON OFF OFF
  140. SW3 OFF OFF OFF ON OFF OFF ON OFF
  141. SW5 OFF OFF OFF OFF OFF OFF ON ON
  142. Note:
  143. - PCIe slots modes: All the PCIe devices work as Root Complex.
  144. - Boot location: NOR flash.
  145. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
  146. 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
  147. NAND boot::
  148. SW1 [1.1] = 0
  149. SW2 [1.1] = 1
  150. SW3 [1:4] = 0001
  151. NOR boot::
  152. SW1 [1.1] = 1
  153. SW2 [1.1] = 0
  154. SW3 [1:4] = 1000
  155. Memory map on B4860QDS
  156. ----------------------
  157. The addresses in brackets are physical addresses.
  158. ============= ============= =============== =======
  159. Start Address End Address Description Size
  160. ============= ============= =============== =======
  161. 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
  162. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
  163. 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
  164. 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
  165. 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
  166. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
  167. 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
  168. 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
  169. 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
  170. 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
  171. 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
  172. 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
  173. 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
  174. 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
  175. 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
  176. 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
  177. 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
  178. 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
  179. 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
  180. 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
  181. 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
  182. 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
  183. 0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
  184. 0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
  185. ============= ============= =============== =======
  186. Memory map on B4420QDS
  187. ----------------------
  188. The addresses in brackets are physical addresses.
  189. ============= ============= =============== =======
  190. Start Address End Address Description Size
  191. ============= ============= =============== =======
  192. 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
  193. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
  194. 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
  195. 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
  196. 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
  197. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
  198. 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
  199. 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
  200. 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
  201. 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
  202. 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
  203. 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
  204. 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
  205. 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
  206. 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
  207. 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
  208. 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
  209. 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
  210. 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
  211. 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
  212. 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
  213. 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
  214. 0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
  215. ============= ============= =============== =======
  216. NOR Flash memory Map on B4860 and B4420QDS
  217. ------------------------------------------
  218. ============= ============= ============================== =========
  219. Start End Definition Size
  220. ============= ============= ============================== =========
  221. 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
  222. 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
  223. 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
  224. 0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
  225. 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
  226. 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
  227. 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
  228. 0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
  229. 0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
  230. 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
  231. 0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
  232. 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
  233. 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
  234. 0xEC000000 0xEC01FFFF RCW (current bank) 128KB
  235. ============= ============= ============================== =========
  236. Various Software configurations/environment variables/commands
  237. --------------------------------------------------------------
  238. The below commands apply to both B4860QDS and B4420QDS.
  239. U-Boot environment variable hwconfig
  240. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  241. The default hwconfig is:
  242. .. code-block:: none
  243. hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
  244. Note: For USB gadget set "dr_mode=peripheral"
  245. FMAN Ucode versions
  246. ^^^^^^^^^^^^^^^^^^^
  247. fsl_fman_ucode_B4860_106_3_6.bin
  248. Switching to alternate bank
  249. ^^^^^^^^^^^^^^^^^^^^^^^^^^^
  250. Commands for switching to alternate bank.
  251. 1. To change from vbank0 to vbank2
  252. .. code-block:: none
  253. => qixis_reset altbank (it will boot using vbank2)
  254. 2. To change from vbank2 to vbank0
  255. .. code-block:: none
  256. => qixis reset (it will boot using vbank0)
  257. To change personality of board
  258. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  259. For changing personality from B4860 to B4420
  260. 1. Boot from vbank0
  261. 2. Flash vbank2 with b4420 rcw and U-Boot
  262. 3. Give following commands to uboot prompt
  263. .. code-block:: none
  264. => mw.b ffdf0040 0x30;
  265. => mw.b ffdf0010 0x00;
  266. => mw.b ffdf0062 0x02;
  267. => mw.b ffdf0050 0x02;
  268. => mw.b ffdf0010 0x30;
  269. => reset
  270. Note:
  271. - Power off cycle will lead to default switch settings.
  272. - 0xffdf0000 is the address of the QIXIS FPGA.
  273. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
  274. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  275. To change from NOR to NAND boot give following command on uboot prompt
  276. .. code-block:: none
  277. => mw.b ffdf0040 0x30
  278. => mw.b ffdf0010 0x00
  279. => mw.b 0xffdf0050 0x08
  280. => mw.b 0xffdf0060 0x82
  281. => mw.b ffdf0061 0x00
  282. => mw.b ffdf0010 0x30
  283. => reset
  284. To change from NAND to NOR boot give following command on uboot prompt:
  285. .. code-block:: none
  286. => mw.b ffdf0040 0x30
  287. => mw.b ffdf0010 0x00
  288. => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
  289. => mw.b 0xffdf0060 0x12
  290. => mw.b ffdf0061 0x01
  291. => mw.b ffdf0010 0x30
  292. => reset
  293. Note:
  294. - Power off cycle will lead to default switch settings.
  295. - 0xffdf0000 is the address of the QIXIS FPGA.
  296. Ethernet interfaces for B4860QDS
  297. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  298. Serdes protocosl tested:
  299. * 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
  300. * 0x2a, 0xb2 (serdes1, serdes2)
  301. When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
  302. SGMII on SGMII riser card.
  303. Under U-Boot these network interfaces are recognized as::
  304. FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
  305. On Linux the interfaces are renamed as::
  306. eth2 -> fm1-gb2
  307. eth3 -> fm1-gb3
  308. eth4 -> fm1-gb4
  309. eth5 -> fm1-gb5
  310. RCW and Ethernet interfaces for B4420QDS
  311. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  312. Serdes protocosl tested:
  313. * 0x18, 0x9e (serdes1, serdes2)
  314. Under U-Boot these network interfaces are recognized as::
  315. FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
  316. On Linux the interfaces are renamed as::
  317. eth2 -> fm1-gb2
  318. eth3 -> fm1-gb3
  319. NAND boot with 2 Stage boot loader
  320. ----------------------------------
  321. PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
  322. SPL further initialise DDR using SPD and environment variables and copy
  323. U-Boot(768 KB) from flash to DDR.
  324. Finally SPL transer control to U-Boot for futher booting.
  325. SPL has following features:
  326. - Executes within 256K
  327. - No relocation required
  328. Run time view of SPL framework during boot:
  329. +----------------------------------------------+
  330. |Area | Address |
  331. +----------------------------------------------+
  332. |Secure boot | 0xFFFC0000 (32KB) |
  333. |headers | |
  334. +----------------------------------------------+
  335. |GD, BD | 0xFFFC8000 (4KB) |
  336. +----------------------------------------------+
  337. |ENV | 0xFFFC9000 (8KB) |
  338. +----------------------------------------------+
  339. |HEAP | 0xFFFCB000 (30KB) |
  340. +----------------------------------------------+
  341. |STACK | 0xFFFD8000 (22KB) |
  342. +----------------------------------------------+
  343. |U-Boot SPL | 0xFFFD8000 (160KB) |
  344. +----------------------------------------------+
  345. NAND Flash memory Map on B4860 and B4420QDS
  346. -------------------------------------------
  347. ============= ============= ============================= =====
  348. Start End Definition Size
  349. ============= ============= ============================= =====
  350. 0x000000 0x0FFFFF U-Boot 1MB
  351. 0x140000 0x15FFFF U-Boot env 128KB
  352. 0x1A0000 0x1BFFFF FMAN Ucode 128KB
  353. ============= ============= ============================= =====