pico-imx7d.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 NXP Semiconductors
  4. */
  5. #include <init.h>
  6. #include <net.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/mx7-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <i2c.h>
  19. #include <miiphy.h>
  20. #include <power/pmic.h>
  21. #include <power/pfuze3000_pmic.h>
  22. #include "../../freescale/common/pfuze.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  25. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  26. #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  27. PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  28. #ifdef CONFIG_SYS_I2C_MXC
  29. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  30. /* I2C4 for PMIC */
  31. static struct i2c_pads_info i2c_pad_info4 = {
  32. .scl = {
  33. .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
  34. .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
  35. .gp = IMX_GPIO_NR(6, 16),
  36. },
  37. .sda = {
  38. .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
  39. .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
  40. .gp = IMX_GPIO_NR(6, 17),
  41. },
  42. };
  43. #endif
  44. int dram_init(void)
  45. {
  46. gd->ram_size = imx_ddr_size();
  47. /* Subtract the defined OPTEE runtime firmware length */
  48. #ifdef CONFIG_OPTEE_TZDRAM_SIZE
  49. gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
  50. #endif
  51. return 0;
  52. }
  53. #if CONFIG_IS_ENABLED(POWER_LEGACY)
  54. #define I2C_PMIC 3
  55. int power_init_board(void)
  56. {
  57. struct pmic *p;
  58. int ret;
  59. unsigned int reg, rev_id;
  60. ret = power_pfuze3000_init(I2C_PMIC);
  61. if (ret)
  62. return ret;
  63. p = pmic_get("PFUZE3000");
  64. ret = pmic_probe(p);
  65. if (ret) {
  66. printf("Warning: Cannot find PMIC PFUZE3000\n");
  67. printf("\tPower consumption is not optimized.\n");
  68. return 0;
  69. }
  70. pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  71. pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  72. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  73. /* disable Low Power Mode during standby mode */
  74. pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  75. reg |= 0x1;
  76. pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  77. /* SW1A/1B mode set to APS/APS */
  78. reg = 0x8;
  79. pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
  80. pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
  81. /* SW1A/1B standby voltage set to 1.025V */
  82. reg = 0xd;
  83. pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
  84. pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
  85. /* decrease SW1B normal voltage to 0.975V */
  86. pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
  87. reg &= ~0x1f;
  88. reg |= PFUZE3000_SW1AB_SETP(975);
  89. pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
  90. return 0;
  91. }
  92. #endif
  93. static iomux_v3_cfg_t const wdog_pads[] = {
  94. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  95. };
  96. static iomux_v3_cfg_t const uart5_pads[] = {
  97. MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  98. MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  99. };
  100. #ifdef CONFIG_FEC_MXC
  101. static int setup_fec(void)
  102. {
  103. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  104. = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  105. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
  106. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  107. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  108. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  109. return set_clk_enet(ENET_125MHZ);
  110. }
  111. int board_phy_config(struct phy_device *phydev)
  112. {
  113. unsigned short val;
  114. /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  117. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  118. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  119. val &= 0xffe7;
  120. val |= 0x18;
  121. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  122. /* introduce tx clock delay */
  123. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  124. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  125. val |= 0x0100;
  126. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  127. if (phydev->drv->config)
  128. phydev->drv->config(phydev);
  129. return 0;
  130. }
  131. #endif
  132. static void setup_iomux_uart(void)
  133. {
  134. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  135. }
  136. int board_early_init_f(void)
  137. {
  138. setup_iomux_uart();
  139. #ifdef CONFIG_SYS_I2C_MXC
  140. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
  141. #endif
  142. return 0;
  143. }
  144. #ifdef CONFIG_DM_VIDEO
  145. void setup_lcd(void)
  146. {
  147. gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
  148. gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
  149. /* Set Brightness to high */
  150. gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
  151. /* Set LCD enable to high */
  152. gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
  153. }
  154. #endif
  155. int board_init(void)
  156. {
  157. /* address of boot parameters */
  158. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  159. #ifdef CONFIG_DM_VIDEO
  160. setup_lcd();
  161. #endif
  162. #ifdef CONFIG_FEC_MXC
  163. setup_fec();
  164. #endif
  165. return 0;
  166. }
  167. int board_late_init(void)
  168. {
  169. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  170. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  171. set_wdog_reset(wdog);
  172. /*
  173. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  174. * since we use PMIC_PWRON to reset the board.
  175. */
  176. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  177. return 0;
  178. }
  179. int checkboard(void)
  180. {
  181. puts("Board: i.MX7D PICOSOM\n");
  182. return 0;
  183. }
  184. static iomux_v3_cfg_t const usb_otg2_pads[] = {
  185. MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  186. };
  187. int board_ehci_hcd_init(int port)
  188. {
  189. switch (port) {
  190. case 0:
  191. break;
  192. case 1:
  193. imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  194. ARRAY_SIZE(usb_otg2_pads));
  195. break;
  196. default:
  197. return -EINVAL;
  198. }
  199. return 0;
  200. }