README 6.9 KB

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  1. Overview
  2. --------
  3. The LS2080A Development System (QDS) is a high-performance computing,
  4. evaluation, and development platform that supports the QorIQ LS2080A
  5. and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
  6. validation and SW development platform for the Freescale LS2080A, LS2088A
  7. processor series, with a complete debugging environment.
  8. LS2080A, LS2088A SoC Overview
  9. --------------------
  10. Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
  11. LS2088A SoC overview.
  12. LS2080AQDS board Overview
  13. -----------------------
  14. - SERDES Connections, 16 lanes supporting:
  15. - PCI Express - 3.0
  16. - SGMII, SGMII 2.5
  17. - QSGMII
  18. - SATA 3.0
  19. - XAUI
  20. - 10GBase-R
  21. - DDR Controller
  22. - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
  23. chip-selects and two DIMM connectors. Support is up to 2133MT/s.
  24. - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
  25. and two DIMM connectors. Support is up to 1600MT/s.
  26. -IFC/Local Bus
  27. - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
  28. - One in-socket 128 MB NOR flash 16-bit data bus
  29. - One 512 MB NAND flash with ECC support
  30. - IFC Test Port
  31. - PromJet Port
  32. - FPGA connection
  33. - USB 3.0
  34. - Two high speed USB 3.0 ports
  35. - First USB 3.0 port configured as Host with Type-A connector
  36. - Second USB 3.0 port configured as OTG with micro-AB connector
  37. - SDHC: PCIe x1 Right Angle connector for supporting following cards
  38. - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
  39. - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
  40. - 4-bit eMMC Card Rev 4.4 (1.8V only)
  41. - 8-bit eMMC Card Rev 4.5 (1.8V only)
  42. - SD Card Rev 2.0 and Rev 3.0
  43. - DSPI: 3 high-speed flash Memory for storage
  44. - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
  45. - 8 MB high-speed flash Memory (up to 104 MHz)
  46. - 512 MB low-speed flash Memory (up to 40 MHz)
  47. - QSPI: via NAND/QSPI Card
  48. - 4 I2C controllers
  49. - Two SATA onboard connectors
  50. - UART
  51. - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
  52. - Two DB9 D-Type connectors supporting one Serial port each
  53. - ARM JTAG support
  54. Memory map from core's view
  55. ----------------------------
  56. 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
  57. 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
  58. 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
  59. 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
  60. 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
  61. 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
  62. 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
  63. Other addresses are either reserved, or not used directly by U-Boot.
  64. This list should be updated when more addresses are used.
  65. IFC region map from core's view
  66. -------------------------------
  67. During boot i.e. IFC Region #1:-
  68. 0x30000000 - 0x37ffffff : 128MB : NOR flash
  69. 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  70. 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  71. After relocate to DDR i.e. IFC Region #2:-
  72. 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  73. 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  74. 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  75. 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  76. 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  77. Booting Options
  78. ---------------
  79. a) Promjet Boot
  80. b) NOR boot
  81. c) NAND boot
  82. d) SD boot
  83. e) QSPI boot
  84. Memory map for NOR boot
  85. -------------------------
  86. Image Flash Offset
  87. RCW+PBI 0x00000000
  88. Boot firmware (U-Boot) 0x00100000
  89. Boot firmware Environment 0x00300000
  90. PPA firmware 0x00400000
  91. Secure Headers 0x00600000
  92. DPAA2 MC 0x00A00000
  93. DPAA2 DPL 0x00D00000
  94. DPAA2 DPC 0x00E00000
  95. Kernel.itb 0x01000000
  96. Memory map for SD boot
  97. -------------------------
  98. Image Flash Offset SD Card
  99. Start Block No.
  100. RCW+PBI 0x00000000 0x00008
  101. Boot firmware (U-Boot) 0x00100000 0x00800
  102. Boot firmware Environment 0x00300000 0x01800
  103. PPA firmware 0x00400000 0x02000
  104. DPAA2 MC 0x00A00000 0x05000
  105. DPAA2 DPL 0x00D00000 0x06800
  106. DPAA2 DPC 0x00E00000 0x07000
  107. Kernel.itb 0x01000000 0x08000
  108. Environment Variables
  109. ---------------------
  110. - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
  111. the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
  112. - mcmemsize: MC DRAM block size. If this variable is not defined
  113. the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
  114. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
  115. -------------------------------------------------------------------
  116. One needs to use appropriate bootargs to boot Linux flavors which do
  117. not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
  118. below:
  119. => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
  120. earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
  121. hugepages=16 mem=2048M'
  122. X-QSGMII-16PORT riser card
  123. ----------------------------
  124. The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
  125. interfaces implemented in PCIe form factor board.
  126. It supports following:
  127. - Card can operate with up to 4 QSGMII lane simultaneously
  128. - Card can operate with up to 8 SGMII lane simultaneously
  129. Supported card configuration
  130. - CSEL : ON ON ON ON
  131. - MSEL1 : ON ON ON ON OFF OFF OFF OFF
  132. - MSEL2 : OFF OFF OFF OFF ON ON ON ON
  133. To enable this card: modify hwconfig to add "xqsgmii" variable.
  134. Supported PHY addresses during SGMII:
  135. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  136. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  137. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  138. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  139. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  140. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  141. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  142. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  143. Mapping DPMACx to PHY during SGMII
  144. DPMAC1 -> PHY1-P0
  145. DPMAC2 -> PHY2-P0
  146. DPMAC3 -> PHY3-P0
  147. DPMAC4 -> PHY4-P0
  148. DPMAC5 -> PHY3-P2
  149. DPMAC6 -> PHY1-P2
  150. DPMAC7 -> PHY4-P1
  151. DPMAC8 -> PHY2-P2
  152. DPMAC9 -> PHY1-P0
  153. DPMAC10 -> PHY2-P0
  154. DPMAC11 -> PHY3-P0
  155. DPMAC12 -> PHY4-P0
  156. DPMAC13 -> PHY3-P2
  157. DPMAC14 -> PHY1-P2
  158. DPMAC15 -> PHY4-P1
  159. DPMAC16 -> PHY2-P2
  160. Supported PHY address during QSGMII
  161. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  162. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  163. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  164. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  165. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  166. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  167. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  168. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  169. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  170. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  171. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  172. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  173. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  174. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  175. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  176. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  177. Mapping DPMACx to PHY during QSGMII
  178. DPMAC1 -> PHY1-P3
  179. DPMAC2 -> PHY1-P2
  180. DPMAC3 -> PHY1-P1
  181. DPMAC4 -> PHY1-P0
  182. DPMAC5 -> PHY2-P3
  183. DPMAC6 -> PHY2-P2
  184. DPMAC7 -> PHY2-P1
  185. DPMAC8 -> PHY2-P0
  186. DPMAC9 -> PHY3-P0
  187. DPMAC10 -> PHY3-P1
  188. DPMAC11 -> PHY3-P2
  189. DPMAC12 -> PHY3-P3
  190. DPMAC13 -> PHY4-P0
  191. DPMAC14 -> PHY4-P1
  192. DPMAC15 -> PHY4-P2
  193. DPMAC16 -> PHY4-P3