README 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124
  1. Tensilica 'xtfpga' Evaluation Boards
  2. ====================================
  3. Tensilica's 'xtfpga' evaluation boards are actually a set of different
  4. boards that share configurations. The following is a list of supported
  5. hardware by this board type:
  6. - XT-AV60 / LX60
  7. - XT-AV110 / LX110
  8. - XT-AV200 / LX200
  9. - ML605
  10. - KC705
  11. All boards provide the following common configurations:
  12. - An Xtensa or Diamond processor core.
  13. - An on-chip-debug (OCD) JTAG interface.
  14. - A 16550 compatible UART and serial port.
  15. - An OpenCores Wishbone 10/100-base-T ethernet interface.
  16. - A 32 char two line LCD display. (except for the LX200)
  17. LX60/LX110/LX200:
  18. - Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
  19. - 128MB / 64MB (LX60) memory
  20. - 16MB / 4MB (LX60) Linear Flash
  21. ML605
  22. - Virtex-6 (XC6VLX240T)
  23. - 512MB DDR3 memory
  24. - 16MB Linear BPI Flash
  25. KC705 (Xilinx)
  26. - Kintex-7 XC7K325T FPGA
  27. - 1GB DDR3 memory
  28. - 128MB Linear BPI Flash
  29. Setting up the Board
  30. --------------------
  31. The serial port defaults to 115200 baud, no parity and 1 stop bit.
  32. A terminal emulator must be set accordingly to see the U-Boot prompt.
  33. Board Configurations LX60/LX110/LX200/ML605/KC705
  34. -------------------------------------------------
  35. The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
  36. the boot mapping and selects from a range of default ethernet MAC
  37. addresses.
  38. Boot Mapping (DIP switch 8):
  39. DIP switch 8 maps the system ROM address space (in which the
  40. reset vector resides) to either SRAM (off, 0, down) or Flash
  41. (on, 1, up). This mapping is implemented in the FPGA bitstream
  42. and cannot be disabled by software, therefore DIP switch 8 is no
  43. available for application use. Note DIP switch 7 is reserved by
  44. Tensilica for future possible hardware use.
  45. Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
  46. tool such as the Xtensa OCD Daemon connected via a suppored probe.
  47. See the tools documentation for supported probes and how to
  48. connect them. Be aware that the board has only 128 KB of SRAM,
  49. therefore U-Boot must fit within this space to debug an image
  50. intended for the Flash. This issues is discussed in a separate
  51. section toward the end.
  52. Mapping to flash allows U-Boot to start on reset, provided it
  53. has been programmed into the first two 64 KB sectors of the Flash.
  54. The Flash is always mapped at a device (memory mapped I/O) address
  55. (the address is board specific and is expressed as CFG_FLASH_BASE).
  56. The device address is used by U-Boot to program the flash, and may
  57. be used to specify an application to run or U-Boot image to boot.
  58. Default MAC Address (DIP switches 1-6):
  59. When the board is first powered on, or after the environment has
  60. been reinitialized, the ethernet MAC address receives a default
  61. value whose least significant 6 bits come from DIP switches 1-6.
  62. The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
  63. according to the DIP switches, where "on"==1 and "off"==0, and
  64. switch 1 is the least-significant bit.
  65. After initial startup, the MAC address is stored in the U-Boot
  66. environment variable 'ethaddr'. The user may change this to any
  67. other address with the "setenv" comamnd. After the environment
  68. has been saved to Flash by the "saveenv" command, this will be
  69. used and the DIP switches no longer consulted. DIP swithes 1-6
  70. may then be used for application purposes.
  71. The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
  72. switch and ways 2-4 control the low three bits of the MAC address.
  73. Limitation of SDRAM Size for OCD Debugging on the LX60
  74. ------------------------------------------------------
  75. The XT-AV60 board has only 128 KB of SDRAM that can be mapped
  76. to the system ROM address space for debugging a ROM image under
  77. OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
  78. or the first 2 sectors of the flash.
  79. This can pose a problem if all the sources are compiled with -O0
  80. for debugging. The code size is then too large, in which case it
  81. would be necessary to temporarily alter the linker script to place
  82. the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
  83. directly there and does not unpack. In practice this is not really
  84. necessary as long as only a limited set of sources need to be
  85. debugged, because the image can still fit into the 128 KB SRAM.
  86. The recommended procedure for debugging is to first build U-Boot
  87. with the default optimization level (-Os), and then touch and
  88. rebuild incrementally with -O0 so that only the touched sources
  89. are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
  90. variable to make.
  91. Because this problem is easy to fall into and difficult to debug
  92. if one doesn't expect it, the linker script provides a link-time
  93. check and fatal error message if the image size exceeds 128 KB.