regs.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
  4. */
  5. #ifndef _XTENSA_REGS_H
  6. #define _XTENSA_REGS_H
  7. /* Special registers */
  8. #define IBREAKA 128
  9. #define DBREAKA 144
  10. #define DBREAKC 160
  11. /* Special names for read-only and write-only interrupt registers */
  12. #define INTREAD 226
  13. #define INTSET 226
  14. #define INTCLEAR 227
  15. /* EXCCAUSE register fields */
  16. #define EXCCAUSE_EXCCAUSE_SHIFT 0
  17. #define EXCCAUSE_EXCCAUSE_MASK 0x3F
  18. #define EXCCAUSE_ILLEGAL_INSTRUCTION 0
  19. #define EXCCAUSE_SYSTEM_CALL 1
  20. #define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
  21. #define EXCCAUSE_LOAD_STORE_ERROR 3
  22. #define EXCCAUSE_LEVEL1_INTERRUPT 4
  23. #define EXCCAUSE_ALLOCA 5
  24. #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
  25. #define EXCCAUSE_SPECULATION 7
  26. #define EXCCAUSE_PRIVILEGED 8
  27. #define EXCCAUSE_UNALIGNED 9
  28. #define EXCCAUSE_INSTR_DATA_ERROR 12
  29. #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13
  30. #define EXCCAUSE_INSTR_ADDR_ERROR 14
  31. #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15
  32. #define EXCCAUSE_ITLB_MISS 16
  33. #define EXCCAUSE_ITLB_MULTIHIT 17
  34. #define EXCCAUSE_ITLB_PRIVILEGE 18
  35. #define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
  36. #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
  37. #define EXCCAUSE_DTLB_MISS 24
  38. #define EXCCAUSE_DTLB_MULTIHIT 25
  39. #define EXCCAUSE_DTLB_PRIVILEGE 26
  40. #define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
  41. #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
  42. #define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
  43. #define EXCCAUSE_COPROCESSOR0_DISABLED 32
  44. #define EXCCAUSE_COPROCESSOR1_DISABLED 33
  45. #define EXCCAUSE_COPROCESSOR2_DISABLED 34
  46. #define EXCCAUSE_COPROCESSOR3_DISABLED 35
  47. #define EXCCAUSE_COPROCESSOR4_DISABLED 36
  48. #define EXCCAUSE_COPROCESSOR5_DISABLED 37
  49. #define EXCCAUSE_COPROCESSOR6_DISABLED 38
  50. #define EXCCAUSE_COPROCESSOR7_DISABLED 39
  51. #define EXCCAUSE_LAST 63
  52. /* PS register fields */
  53. #define PS_WOE_BIT 18
  54. #define PS_CALLINC_SHIFT 16
  55. #define PS_CALLINC_MASK 0x00030000
  56. #define PS_OWB_SHIFT 8
  57. #define PS_OWB_MASK 0x00000F00
  58. #define PS_RING_SHIFT 6
  59. #define PS_RING_MASK 0x000000C0
  60. #define PS_UM_BIT 5
  61. #define PS_EXCM_BIT 4
  62. #define PS_INTLEVEL_SHIFT 0
  63. #define PS_INTLEVEL_MASK 0x0000000F
  64. /* DBREAKCn register fields */
  65. #define DBREAKC_MASK_BIT 0
  66. #define DBREAKC_MASK_MASK 0x0000003F
  67. #define DBREAKC_LOAD_BIT 30
  68. #define DBREAKC_LOAD_MASK 0x40000000
  69. #define DBREAKC_STOR_BIT 31
  70. #define DBREAKC_STOR_MASK 0x80000000
  71. /* DEBUGCAUSE register fields */
  72. #define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
  73. #define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
  74. #define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
  75. #define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
  76. #define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
  77. #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
  78. #endif /* _XTENSA_SPECREG_H */