tie-asm.h 6.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * This header file contains assembly-language definitions (assembly
  4. * macros, etc.) for this specific Xtensa processor's TIE extensions
  5. * and options. It is customized to this Xtensa processor configuration.
  6. * This file is autogenerated, please do not edit.
  7. *
  8. * Copyright (C) 1999-2015 Cadence Design Systems Inc.
  9. */
  10. #ifndef _XTENSA_CORE_TIE_ASM_H
  11. #define _XTENSA_CORE_TIE_ASM_H
  12. /* Selection parameter values for save-area save/restore macros: */
  13. /* Option vs. TIE: */
  14. #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
  15. #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
  16. #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
  17. /* Whether used automatically by compiler: */
  18. #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
  19. #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
  20. #define XTHAL_SAS_ANYCC 0x000C /* both of the above */
  21. /* ABI handling across function calls: */
  22. #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
  23. #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
  24. #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
  25. #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
  26. /* Misc */
  27. #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
  28. #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
  29. | ((ccuse) & XTHAL_SAS_ANYCC) \
  30. | ((abi) & XTHAL_SAS_ANYABI) )
  31. /*
  32. * Macro to store all non-coprocessor (extra) custom TIE and optional state
  33. * (not including zero-overhead loop registers).
  34. * Required parameters:
  35. * ptr Save area pointer address register (clobbered)
  36. * (register must contain a 4 byte aligned address).
  37. * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
  38. * registers are clobbered, the remaining are unused).
  39. * Optional parameters:
  40. * continue If macro invoked as part of a larger store sequence, set to 1
  41. * if this is not the first in the sequence. Defaults to 0.
  42. * ofs Offset from start of larger sequence (from value of first ptr
  43. * in sequence) at which to store. Defaults to next available space
  44. * (or 0 if <continue> is 0).
  45. * select Select what category(ies) of registers to store, as a bitmask
  46. * (see XTHAL_SAS_xxx constants). Defaults to all registers.
  47. * alloc Select what category(ies) of registers to allocate; if any
  48. * category is selected here that is not in <select>, space for
  49. * the corresponding registers is skipped without doing any store.
  50. */
  51. .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
  52. xchal_sa_start \continue, \ofs
  53. // Optional caller-saved registers used by default by the compiler:
  54. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
  55. xchal_sa_align \ptr, 0, 1016, 4, 4
  56. rsr.ACCLO \at1 // MAC16 option
  57. s32i \at1, \ptr, .Lxchal_ofs_+0
  58. rsr.ACCHI \at1 // MAC16 option
  59. s32i \at1, \ptr, .Lxchal_ofs_+4
  60. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  61. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  62. xchal_sa_align \ptr, 0, 1016, 4, 4
  63. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  64. .endif
  65. // Optional caller-saved registers not used by default by the compiler:
  66. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
  67. xchal_sa_align \ptr, 0, 1004, 4, 4
  68. rsr.SCOMPARE1 \at1 // conditional store option
  69. s32i \at1, \ptr, .Lxchal_ofs_+0
  70. rsr.M0 \at1 // MAC16 option
  71. s32i \at1, \ptr, .Lxchal_ofs_+4
  72. rsr.M1 \at1 // MAC16 option
  73. s32i \at1, \ptr, .Lxchal_ofs_+8
  74. rsr.M2 \at1 // MAC16 option
  75. s32i \at1, \ptr, .Lxchal_ofs_+12
  76. rsr.M3 \at1 // MAC16 option
  77. s32i \at1, \ptr, .Lxchal_ofs_+16
  78. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  79. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  80. xchal_sa_align \ptr, 0, 1004, 4, 4
  81. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  82. .endif
  83. .endm // xchal_ncp_store
  84. /*
  85. * Macro to load all non-coprocessor (extra) custom TIE and optional state
  86. * (not including zero-overhead loop registers).
  87. * Required parameters:
  88. * ptr Save area pointer address register (clobbered)
  89. * (register must contain a 4 byte aligned address).
  90. * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
  91. * registers are clobbered, the remaining are unused).
  92. * Optional parameters:
  93. * continue If macro invoked as part of a larger load sequence, set to 1
  94. * if this is not the first in the sequence. Defaults to 0.
  95. * ofs Offset from start of larger sequence (from value of first ptr
  96. * in sequence) at which to load. Defaults to next available space
  97. * (or 0 if <continue> is 0).
  98. * select Select what category(ies) of registers to load, as a bitmask
  99. * (see XTHAL_SAS_xxx constants). Defaults to all registers.
  100. * alloc Select what category(ies) of registers to allocate; if any
  101. * category is selected here that is not in <select>, space for
  102. * the corresponding registers is skipped without doing any load.
  103. */
  104. .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
  105. xchal_sa_start \continue, \ofs
  106. // Optional caller-saved registers used by default by the compiler:
  107. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
  108. xchal_sa_align \ptr, 0, 1016, 4, 4
  109. l32i \at1, \ptr, .Lxchal_ofs_+0
  110. wsr.ACCLO \at1 // MAC16 option
  111. l32i \at1, \ptr, .Lxchal_ofs_+4
  112. wsr.ACCHI \at1 // MAC16 option
  113. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  114. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  115. xchal_sa_align \ptr, 0, 1016, 4, 4
  116. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  117. .endif
  118. // Optional caller-saved registers not used by default by the compiler:
  119. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
  120. xchal_sa_align \ptr, 0, 1004, 4, 4
  121. l32i \at1, \ptr, .Lxchal_ofs_+0
  122. wsr.SCOMPARE1 \at1 // conditional store option
  123. l32i \at1, \ptr, .Lxchal_ofs_+4
  124. wsr.M0 \at1 // MAC16 option
  125. l32i \at1, \ptr, .Lxchal_ofs_+8
  126. wsr.M1 \at1 // MAC16 option
  127. l32i \at1, \ptr, .Lxchal_ofs_+12
  128. wsr.M2 \at1 // MAC16 option
  129. l32i \at1, \ptr, .Lxchal_ofs_+16
  130. wsr.M3 \at1 // MAC16 option
  131. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  132. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  133. xchal_sa_align \ptr, 0, 1004, 4, 4
  134. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  135. .endif
  136. .endm // xchal_ncp_load
  137. #define XCHAL_NCP_NUM_ATMPS 1
  138. #define XCHAL_SA_NUM_ATMPS 1
  139. #endif /*_XTENSA_CORE_TIE_ASM_H*/