tie-asm.h 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * This header file contains assembly-language definitions (assembly
  4. * macros, etc.) for this specific Xtensa processor's TIE extensions
  5. * and options. It is customized to this Xtensa processor configuration.
  6. * This file is autogenerated, please do not edit.
  7. *
  8. * Copyright (C) 1999-2010 Tensilica Inc.
  9. */
  10. #ifndef _XTENSA_CORE_TIE_ASM_H
  11. #define _XTENSA_CORE_TIE_ASM_H
  12. /* Selection parameter values for save-area save/restore macros: */
  13. /* Option vs. TIE: */
  14. #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
  15. #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
  16. #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
  17. /* Whether used automatically by compiler: */
  18. #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
  19. #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
  20. #define XTHAL_SAS_ANYCC 0x000C /* both of the above */
  21. /* ABI handling across function calls: */
  22. #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
  23. #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
  24. #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
  25. #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
  26. /* Misc */
  27. #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
  28. #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
  29. | ((ccuse) & XTHAL_SAS_ANYCC) \
  30. | ((abi) & XTHAL_SAS_ANYABI) )
  31. /*
  32. * Macro to save all non-coprocessor (extra) custom TIE and optional state
  33. * (not including zero-overhead loop registers).
  34. * Required parameters:
  35. * ptr Save area pointer address register (clobbered)
  36. * (register must contain a 4 byte aligned address).
  37. * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
  38. * registers are clobbered, the remaining are unused).
  39. * Optional parameters:
  40. * continue If macro invoked as part of a larger store sequence, set to 1
  41. * if this is not the first in the sequence. Defaults to 0.
  42. * ofs Offset from start of larger sequence (from value of first ptr
  43. * in sequence) at which to store. Defaults to next available space
  44. * (or 0 if <continue> is 0).
  45. * select Select what category(ies) of registers to store, as a bitmask
  46. * (see XTHAL_SAS_xxx constants). Defaults to all registers.
  47. * alloc Select what category(ies) of registers to allocate; if any
  48. * category is selected here that is not in <select>, space for
  49. * the corresponding registers is skipped without doing any store.
  50. */
  51. .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
  52. xchal_sa_start \continue, \ofs
  53. // Optional global register used by default by the compiler:
  54. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
  55. xchal_sa_align \ptr, 0, 1020, 4, 4
  56. rur.THREADPTR \at1 // threadptr option
  57. s32i \at1, \ptr, .Lxchal_ofs_+0
  58. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  59. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
  60. xchal_sa_align \ptr, 0, 1020, 4, 4
  61. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  62. .endif
  63. // Optional caller-saved registers used by default by the compiler:
  64. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
  65. xchal_sa_align \ptr, 0, 1016, 4, 4
  66. rsr \at1, ACCLO // MAC16 option
  67. s32i \at1, \ptr, .Lxchal_ofs_+0
  68. rsr \at1, ACCHI // MAC16 option
  69. s32i \at1, \ptr, .Lxchal_ofs_+4
  70. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  71. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  72. xchal_sa_align \ptr, 0, 1016, 4, 4
  73. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  74. .endif
  75. // Optional caller-saved registers not used by default by the compiler:
  76. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
  77. xchal_sa_align \ptr, 0, 1004, 4, 4
  78. rsr \at1, M0 // MAC16 option
  79. s32i \at1, \ptr, .Lxchal_ofs_+0
  80. rsr \at1, M1 // MAC16 option
  81. s32i \at1, \ptr, .Lxchal_ofs_+4
  82. rsr \at1, M2 // MAC16 option
  83. s32i \at1, \ptr, .Lxchal_ofs_+8
  84. rsr \at1, M3 // MAC16 option
  85. s32i \at1, \ptr, .Lxchal_ofs_+12
  86. rsr \at1, SCOMPARE1 // conditional store option
  87. s32i \at1, \ptr, .Lxchal_ofs_+16
  88. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  89. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  90. xchal_sa_align \ptr, 0, 1004, 4, 4
  91. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  92. .endif
  93. .endm // xchal_ncp_store
  94. /*
  95. * Macro to restore all non-coprocessor (extra) custom TIE and optional state
  96. * (not including zero-overhead loop registers).
  97. * Required parameters:
  98. * ptr Save area pointer address register (clobbered)
  99. * (register must contain a 4 byte aligned address).
  100. * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
  101. * registers are clobbered, the remaining are unused).
  102. * Optional parameters:
  103. * continue If macro invoked as part of a larger load sequence, set to 1
  104. * if this is not the first in the sequence. Defaults to 0.
  105. * ofs Offset from start of larger sequence (from value of first ptr
  106. * in sequence) at which to load. Defaults to next available space
  107. * (or 0 if <continue> is 0).
  108. * select Select what category(ies) of registers to load, as a bitmask
  109. * (see XTHAL_SAS_xxx constants). Defaults to all registers.
  110. * alloc Select what category(ies) of registers to allocate; if any
  111. * category is selected here that is not in <select>, space for
  112. * the corresponding registers is skipped without doing any load.
  113. */
  114. .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
  115. xchal_sa_start \continue, \ofs
  116. // Optional global register used by default by the compiler:
  117. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
  118. xchal_sa_align \ptr, 0, 1020, 4, 4
  119. l32i \at1, \ptr, .Lxchal_ofs_+0
  120. wur.THREADPTR \at1 // threadptr option
  121. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  122. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
  123. xchal_sa_align \ptr, 0, 1020, 4, 4
  124. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  125. .endif
  126. // Optional caller-saved registers used by default by the compiler:
  127. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
  128. xchal_sa_align \ptr, 0, 1016, 4, 4
  129. l32i \at1, \ptr, .Lxchal_ofs_+0
  130. wsr \at1, ACCLO // MAC16 option
  131. l32i \at1, \ptr, .Lxchal_ofs_+4
  132. wsr \at1, ACCHI // MAC16 option
  133. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  134. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  135. xchal_sa_align \ptr, 0, 1016, 4, 4
  136. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  137. .endif
  138. // Optional caller-saved registers not used by default by the compiler:
  139. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
  140. xchal_sa_align \ptr, 0, 1004, 4, 4
  141. l32i \at1, \ptr, .Lxchal_ofs_+0
  142. wsr \at1, M0 // MAC16 option
  143. l32i \at1, \ptr, .Lxchal_ofs_+4
  144. wsr \at1, M1 // MAC16 option
  145. l32i \at1, \ptr, .Lxchal_ofs_+8
  146. wsr \at1, M2 // MAC16 option
  147. l32i \at1, \ptr, .Lxchal_ofs_+12
  148. wsr \at1, M3 // MAC16 option
  149. l32i \at1, \ptr, .Lxchal_ofs_+16
  150. wsr \at1, SCOMPARE1 // conditional store option
  151. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  152. .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
  153. xchal_sa_align \ptr, 0, 1004, 4, 4
  154. .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
  155. .endif
  156. .endm // xchal_ncp_load
  157. #define XCHAL_NCP_NUM_ATMPS 1
  158. #define XCHAL_SA_NUM_ATMPS 1
  159. #endif /*_XTENSA_CORE_TIE_ASM_H*/