tie.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * This header file describes this specific Xtensa processor's TIE extensions
  4. * that extend basic Xtensa core functionality. It is customized to this
  5. * Xtensa processor configuration.
  6. * This file is autogenerated, please do not edit.
  7. *
  8. * Copyright (C) 1999-2007 Tensilica Inc.
  9. */
  10. #ifndef _XTENSA_CORE_TIE_H
  11. #define _XTENSA_CORE_TIE_H
  12. #define XCHAL_CP_NUM 1 /* number of coprocessors */
  13. #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
  14. #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
  15. #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
  16. /* Basic parameters of each coprocessor: */
  17. #define XCHAL_CP7_NAME "XTIOP"
  18. #define XCHAL_CP7_IDENT XTIOP
  19. #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
  20. #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
  21. #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
  22. /* Filler info for unassigned coprocessors, to simplify arrays etc: */
  23. #define XCHAL_CP0_SA_SIZE 0
  24. #define XCHAL_CP0_SA_ALIGN 1
  25. #define XCHAL_CP1_SA_SIZE 0
  26. #define XCHAL_CP1_SA_ALIGN 1
  27. #define XCHAL_CP2_SA_SIZE 0
  28. #define XCHAL_CP2_SA_ALIGN 1
  29. #define XCHAL_CP3_SA_SIZE 0
  30. #define XCHAL_CP3_SA_ALIGN 1
  31. #define XCHAL_CP4_SA_SIZE 0
  32. #define XCHAL_CP4_SA_ALIGN 1
  33. #define XCHAL_CP5_SA_SIZE 0
  34. #define XCHAL_CP5_SA_ALIGN 1
  35. #define XCHAL_CP6_SA_SIZE 0
  36. #define XCHAL_CP6_SA_ALIGN 1
  37. /* Save area for non-coprocessor optional and custom (TIE) state: */
  38. #define XCHAL_NCP_SA_SIZE 32
  39. #define XCHAL_NCP_SA_ALIGN 4
  40. /* Total save area for optional and custom state (NCP + CPn): */
  41. #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
  42. #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
  43. /*
  44. * Detailed contents of save areas.
  45. * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
  46. * before expanding the XCHAL_xxx_SA_LIST() macros.
  47. *
  48. * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
  49. * dbnum,base,regnum,bitsz,gapsz,reset,x...)
  50. *
  51. * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
  52. * ccused = set if used by compiler without special options or code
  53. * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
  54. * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
  55. * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
  56. * name = lowercase reg name (no quotes)
  57. * galign = group byte alignment (power of 2) (galign >= align)
  58. * align = register byte alignment (power of 2)
  59. * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
  60. * (not including any pad bytes required to galign this or next reg)
  61. * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
  62. * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
  63. * regnum = reg index in regfile, or special/TIE-user reg number
  64. * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
  65. * gapsz = intervening bits, if bitsz bits not stored contiguously
  66. * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
  67. * reset = register reset value (or 0 if undefined at reset)
  68. * x = reserved for future use (0 until then)
  69. *
  70. * To filter out certain registers, e.g. to expand only the non-global
  71. * registers used by the compiler, you can do something like this:
  72. *
  73. * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
  74. * #define SELCC0(p...)
  75. * #define SELCC1(abikind,p...) SELAK##abikind(p)
  76. * #define SELAK0(p...) REG(p)
  77. * #define SELAK1(p...) REG(p)
  78. * #define SELAK2(p...)
  79. * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
  80. * ...what you want to expand...
  81. */
  82. #define XCHAL_NCP_SA_NUM 8
  83. #define XCHAL_NCP_SA_LIST(s) \
  84. XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
  85. XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
  86. XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
  87. XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
  88. XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
  89. XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
  90. XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
  91. XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
  92. #define XCHAL_CP0_SA_NUM 0
  93. #define XCHAL_CP0_SA_LIST(s) /* empty */
  94. #define XCHAL_CP1_SA_NUM 0
  95. #define XCHAL_CP1_SA_LIST(s) /* empty */
  96. #define XCHAL_CP2_SA_NUM 0
  97. #define XCHAL_CP2_SA_LIST(s) /* empty */
  98. #define XCHAL_CP3_SA_NUM 0
  99. #define XCHAL_CP3_SA_LIST(s) /* empty */
  100. #define XCHAL_CP4_SA_NUM 0
  101. #define XCHAL_CP4_SA_LIST(s) /* empty */
  102. #define XCHAL_CP5_SA_NUM 0
  103. #define XCHAL_CP5_SA_LIST(s) /* empty */
  104. #define XCHAL_CP6_SA_NUM 0
  105. #define XCHAL_CP6_SA_LIST(s) /* empty */
  106. #define XCHAL_CP7_SA_NUM 0
  107. #define XCHAL_CP7_SA_LIST(s) /* empty */
  108. /* Byte length of instruction from its first nibble (op0 field), per FLIX. */
  109. #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
  110. #endif /*_XTENSA_CORE_TIE_H*/