tie-asm.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * This header file contains assembly-language definitions (assembly
  4. * macros, etc.) for this specific Xtensa processor's TIE extensions
  5. * and options. It is customized to this Xtensa processor configuration.
  6. * This file is autogenerated, please do not edit.
  7. *
  8. * Copyright (C) 1999-2007 Tensilica Inc.
  9. */
  10. #ifndef _XTENSA_CORE_TIE_ASM_H
  11. #define _XTENSA_CORE_TIE_ASM_H
  12. /* Selection parameter values for save-area save/restore macros: */
  13. /* Option vs. TIE: */
  14. #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
  15. #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
  16. /* Whether used automatically by compiler: */
  17. #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
  18. #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
  19. /* ABI handling across function calls: */
  20. #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
  21. #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
  22. #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
  23. /* Misc */
  24. #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
  25. /* Macro to save all non-coprocessor (extra) custom TIE and optional state
  26. * (not including zero-overhead loop registers).
  27. * Save area ptr (clobbered): ptr (1 byte aligned)
  28. * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
  29. */
  30. .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
  31. xchal_sa_start \continue, \ofs
  32. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  33. xchal_sa_align \ptr, 0, 1024-8, 4, 4
  34. rsr \at1, ACCLO // MAC16 accumulator
  35. rsr \at2, ACCHI
  36. s32i \at1, \ptr, .Lxchal_ofs_ + 0
  37. s32i \at2, \ptr, .Lxchal_ofs_ + 4
  38. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  39. .endif
  40. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  41. xchal_sa_align \ptr, 0, 1024-16, 4, 4
  42. rsr \at1, M0 // MAC16 registers
  43. rsr \at2, M1
  44. s32i \at1, \ptr, .Lxchal_ofs_ + 0
  45. s32i \at2, \ptr, .Lxchal_ofs_ + 4
  46. rsr \at1, M2
  47. rsr \at2, M3
  48. s32i \at1, \ptr, .Lxchal_ofs_ + 8
  49. s32i \at2, \ptr, .Lxchal_ofs_ + 12
  50. .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
  51. .endif
  52. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  53. xchal_sa_align \ptr, 0, 1024-4, 4, 4
  54. rsr \at1, SCOMPARE1 // conditional store option
  55. s32i \at1, \ptr, .Lxchal_ofs_ + 0
  56. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  57. .endif
  58. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
  59. xchal_sa_align \ptr, 0, 1024-4, 4, 4
  60. rur \at1, THREADPTR // threadptr option
  61. s32i \at1, \ptr, .Lxchal_ofs_ + 0
  62. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  63. .endif
  64. .endm // xchal_ncp_store
  65. /* Macro to save all non-coprocessor (extra) custom TIE and optional state
  66. * (not including zero-overhead loop registers).
  67. * Save area ptr (clobbered): ptr (1 byte aligned)
  68. * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
  69. */
  70. .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
  71. xchal_sa_start \continue, \ofs
  72. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  73. xchal_sa_align \ptr, 0, 1024-8, 4, 4
  74. l32i \at1, \ptr, .Lxchal_ofs_ + 0
  75. l32i \at2, \ptr, .Lxchal_ofs_ + 4
  76. wsr \at1, ACCLO // MAC16 accumulator
  77. wsr \at2, ACCHI
  78. .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  79. .endif
  80. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  81. xchal_sa_align \ptr, 0, 1024-16, 4, 4
  82. l32i \at1, \ptr, .Lxchal_ofs_ + 0
  83. l32i \at2, \ptr, .Lxchal_ofs_ + 4
  84. wsr \at1, M0 // MAC16 registers
  85. wsr \at2, M1
  86. l32i \at1, \ptr, .Lxchal_ofs_ + 8
  87. l32i \at2, \ptr, .Lxchal_ofs_ + 12
  88. wsr \at1, M2
  89. wsr \at2, M3
  90. .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
  91. .endif
  92. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  93. xchal_sa_align \ptr, 0, 1024-4, 4, 4
  94. l32i \at1, \ptr, .Lxchal_ofs_ + 0
  95. wsr \at1, SCOMPARE1 // conditional store option
  96. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  97. .endif
  98. .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
  99. xchal_sa_align \ptr, 0, 1024-4, 4, 4
  100. l32i \at1, \ptr, .Lxchal_ofs_ + 0
  101. wur \at1, THREADPTR // threadptr option
  102. .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  103. .endif
  104. .endm // xchal_ncp_load
  105. #define XCHAL_NCP_NUM_ATMPS 2
  106. #define XCHAL_SA_NUM_ATMPS 2
  107. #endif /*_XTENSA_CORE_TIE_ASM_H*/