core.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Xtensa processor core configuration information.
  4. * This file is autogenerated, please do not edit.
  5. *
  6. * Copyright (C) 1999-2007 Tensilica Inc.
  7. */
  8. #ifndef _XTENSA_CORE_CONFIGURATION_H
  9. #define _XTENSA_CORE_CONFIGURATION_H
  10. /****************************************************************************
  11. Parameters Useful for Any Code, USER or PRIVILEGED
  12. ****************************************************************************/
  13. /*
  14. * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
  15. * configured, and a value of 0 otherwise. These macros are always defined.
  16. */
  17. /*----------------------------------------------------------------------
  18. ISA
  19. ----------------------------------------------------------------------*/
  20. #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
  21. #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
  22. #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
  23. #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
  24. #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
  25. #define XCHAL_HAVE_DEBUG 1 /* debug option */
  26. #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
  27. #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
  28. #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
  29. #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
  30. #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
  31. #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
  32. #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
  33. #define XCHAL_HAVE_MUL32 1 /* MULL instruction */
  34. #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
  35. #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
  36. #define XCHAL_HAVE_L32R 1 /* L32R instruction */
  37. #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
  38. #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
  39. #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
  40. #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
  41. #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
  42. #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
  43. #define XCHAL_HAVE_ABS 1 /* ABS instruction */
  44. /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
  45. /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
  46. #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
  47. #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
  48. #define XCHAL_HAVE_SPECULATION 0 /* speculation */
  49. #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
  50. #define XCHAL_NUM_CONTEXTS 1 /* */
  51. #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
  52. #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
  53. #define XCHAL_HAVE_PRID 1 /* processor ID register */
  54. #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
  55. #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
  56. #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
  57. #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
  58. #define XCHAL_HAVE_MAC16 1 /* MAC16 package */
  59. #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
  60. #define XCHAL_HAVE_FP 0 /* floating point pkg */
  61. #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
  62. #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
  63. #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
  64. /*----------------------------------------------------------------------
  65. MISC
  66. ----------------------------------------------------------------------*/
  67. #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
  68. #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
  69. #define XCHAL_DATA_WIDTH 4 /* data width in bytes */
  70. /* In T1050, applies to selected core load and store instructions (see ISA): */
  71. #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
  72. #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
  73. #define XCHAL_SW_VERSION 701001 /* sw version of this header */
  74. #define XCHAL_CORE_ID "dc232b" /* alphanum core name
  75. (CoreID) set in the Xtensa
  76. Processor Generator */
  77. #define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)"
  78. #define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */
  79. /*
  80. * These definitions describe the hardware targeted by this software.
  81. */
  82. #define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/
  83. #define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/
  84. #define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */
  85. #define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */
  86. #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
  87. #define XCHAL_HW_VERSION 221001 /* major*100+minor */
  88. #define XCHAL_HW_REL_LX2 1
  89. #define XCHAL_HW_REL_LX2_1 1
  90. #define XCHAL_HW_REL_LX2_1_1 1
  91. #define XCHAL_HW_CONFIGID_RELIABLE 1
  92. /* If software targets a *range* of hardware versions, these are the bounds: */
  93. #define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */
  94. #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
  95. #define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */
  96. #define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */
  97. #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
  98. #define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
  99. /*----------------------------------------------------------------------
  100. CACHE
  101. ----------------------------------------------------------------------*/
  102. #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
  103. #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
  104. #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
  105. #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
  106. #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
  107. #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
  108. #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
  109. /****************************************************************************
  110. Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  111. ****************************************************************************/
  112. #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
  113. /*----------------------------------------------------------------------
  114. CACHE
  115. ----------------------------------------------------------------------*/
  116. #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
  117. /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
  118. /* Number of cache sets in log2(lines per way): */
  119. #define XCHAL_ICACHE_SETWIDTH 7
  120. #define XCHAL_DCACHE_SETWIDTH 7
  121. /* Cache set associativity (number of ways): */
  122. #define XCHAL_ICACHE_WAYS 4
  123. #define XCHAL_DCACHE_WAYS 4
  124. /* Cache features: */
  125. #define XCHAL_ICACHE_LINE_LOCKABLE 1
  126. #define XCHAL_DCACHE_LINE_LOCKABLE 1
  127. #define XCHAL_ICACHE_ECC_PARITY 0
  128. #define XCHAL_DCACHE_ECC_PARITY 0
  129. /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
  130. #define XCHAL_CA_BITS 4
  131. /*----------------------------------------------------------------------
  132. INTERNAL I/D RAM/ROMs and XLMI
  133. ----------------------------------------------------------------------*/
  134. #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
  135. #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
  136. #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
  137. #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
  138. #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
  139. #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
  140. /*----------------------------------------------------------------------
  141. INTERRUPTS and TIMERS
  142. ----------------------------------------------------------------------*/
  143. #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
  144. #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
  145. #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
  146. #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
  147. #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
  148. #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
  149. #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
  150. #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
  151. #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
  152. (not including level zero) */
  153. #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
  154. /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
  155. /* Masks of interrupts at each interrupt level: */
  156. #define XCHAL_INTLEVEL1_MASK 0x001F80FF
  157. #define XCHAL_INTLEVEL2_MASK 0x00000100
  158. #define XCHAL_INTLEVEL3_MASK 0x00200E00
  159. #define XCHAL_INTLEVEL4_MASK 0x00001000
  160. #define XCHAL_INTLEVEL5_MASK 0x00002000
  161. #define XCHAL_INTLEVEL6_MASK 0x00000000
  162. #define XCHAL_INTLEVEL7_MASK 0x00004000
  163. /* Masks of interrupts at each range 1..n of interrupt levels: */
  164. #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
  165. #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
  166. #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
  167. #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
  168. #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
  169. #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
  170. #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
  171. /* Level of each interrupt: */
  172. #define XCHAL_INT0_LEVEL 1
  173. #define XCHAL_INT1_LEVEL 1
  174. #define XCHAL_INT2_LEVEL 1
  175. #define XCHAL_INT3_LEVEL 1
  176. #define XCHAL_INT4_LEVEL 1
  177. #define XCHAL_INT5_LEVEL 1
  178. #define XCHAL_INT6_LEVEL 1
  179. #define XCHAL_INT7_LEVEL 1
  180. #define XCHAL_INT8_LEVEL 2
  181. #define XCHAL_INT9_LEVEL 3
  182. #define XCHAL_INT10_LEVEL 3
  183. #define XCHAL_INT11_LEVEL 3
  184. #define XCHAL_INT12_LEVEL 4
  185. #define XCHAL_INT13_LEVEL 5
  186. #define XCHAL_INT14_LEVEL 7
  187. #define XCHAL_INT15_LEVEL 1
  188. #define XCHAL_INT16_LEVEL 1
  189. #define XCHAL_INT17_LEVEL 1
  190. #define XCHAL_INT18_LEVEL 1
  191. #define XCHAL_INT19_LEVEL 1
  192. #define XCHAL_INT20_LEVEL 1
  193. #define XCHAL_INT21_LEVEL 3
  194. #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
  195. #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
  196. #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
  197. EXCSAVE/EPS/EPC_n, RFI n) */
  198. /* Type of each interrupt: */
  199. #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  200. #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  201. #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  202. #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  203. #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  204. #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  205. #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
  206. #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
  207. #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  208. #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  209. #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
  210. #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
  211. #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  212. #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
  213. #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
  214. #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  215. #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  216. #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  217. #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  218. #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  219. #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  220. #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  221. /* Masks of interrupts for each type of interrupt: */
  222. #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
  223. #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
  224. #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
  225. #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
  226. #define XCHAL_INTTYPE_MASK_TIMER 0x00002440
  227. #define XCHAL_INTTYPE_MASK_NMI 0x00004000
  228. #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
  229. /* Interrupt numbers assigned to specific interrupt sources: */
  230. #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
  231. #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
  232. #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
  233. #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
  234. #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
  235. /* Interrupt numbers for levels at which only one interrupt is configured: */
  236. #define XCHAL_INTLEVEL2_NUM 8
  237. #define XCHAL_INTLEVEL4_NUM 12
  238. #define XCHAL_INTLEVEL5_NUM 13
  239. #define XCHAL_INTLEVEL7_NUM 14
  240. /* (There are many interrupts each at level(s) 1, 3.) */
  241. /*
  242. * External interrupt vectors/levels.
  243. * These macros describe how Xtensa processor interrupt numbers
  244. * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
  245. * map to external BInterrupt<n> pins, for those interrupts
  246. * configured as external (level-triggered, edge-triggered, or NMI).
  247. * See the Xtensa processor databook for more details.
  248. */
  249. /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
  250. #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
  251. #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
  252. #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
  253. #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
  254. #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
  255. #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
  256. #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
  257. #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
  258. #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
  259. #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
  260. #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
  261. #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
  262. #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
  263. #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
  264. #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
  265. #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
  266. #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
  267. /*----------------------------------------------------------------------
  268. EXCEPTIONS and VECTORS
  269. ----------------------------------------------------------------------*/
  270. #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
  271. number: 1 == XEA1 (old)
  272. 2 == XEA2 (new)
  273. 0 == XEAX (extern) */
  274. #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
  275. #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
  276. #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
  277. #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
  278. #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
  279. #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
  280. #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
  281. #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
  282. #define XCHAL_VECBASE_RESET_PADDR 0x00000000
  283. #define XCHAL_RESET_VECBASE_OVERLAP 0
  284. #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
  285. #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
  286. #define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
  287. #define XCHAL_RESET_VECTOR1_PADDR 0x00000500
  288. #define XCHAL_RESET_VECTOR_VADDR 0xFE000000
  289. #define XCHAL_RESET_VECTOR_PADDR 0xFE000000
  290. #define XCHAL_USER_VECOFS 0x00000340
  291. #define XCHAL_USER_VECTOR_VADDR 0xD0000340
  292. #define XCHAL_USER_VECTOR_PADDR 0x00000340
  293. #define XCHAL_KERNEL_VECOFS 0x00000300
  294. #define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
  295. #define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
  296. #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
  297. #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
  298. #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
  299. #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
  300. #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
  301. #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
  302. #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
  303. #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
  304. #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
  305. #define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
  306. #define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
  307. #define XCHAL_INTLEVEL2_VECOFS 0x00000180
  308. #define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180
  309. #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180
  310. #define XCHAL_INTLEVEL3_VECOFS 0x000001C0
  311. #define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0
  312. #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0
  313. #define XCHAL_INTLEVEL4_VECOFS 0x00000200
  314. #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200
  315. #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200
  316. #define XCHAL_INTLEVEL5_VECOFS 0x00000240
  317. #define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240
  318. #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240
  319. #define XCHAL_INTLEVEL6_VECOFS 0x00000280
  320. #define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280
  321. #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280
  322. #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
  323. #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
  324. #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
  325. #define XCHAL_NMI_VECOFS 0x000002C0
  326. #define XCHAL_NMI_VECTOR_VADDR 0xD00002C0
  327. #define XCHAL_NMI_VECTOR_PADDR 0x000002C0
  328. #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
  329. #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
  330. #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
  331. /*----------------------------------------------------------------------
  332. DEBUG
  333. ----------------------------------------------------------------------*/
  334. #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
  335. #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
  336. #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
  337. #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
  338. /*----------------------------------------------------------------------
  339. MMU
  340. ----------------------------------------------------------------------*/
  341. /* See core-matmap.h header file for more details. */
  342. #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
  343. #define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
  344. #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
  345. #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
  346. #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
  347. #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
  348. #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
  349. [autorefill] and protection)
  350. usable for an MMU-based OS */
  351. /* If none of the above last 4 are set, it's a custom TLB configuration. */
  352. #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
  353. #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
  354. #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
  355. #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
  356. #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
  357. #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
  358. #endif /* _XTENSA_CORE_CONFIGURATION_H */