fsl_corenet_serdes.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <log.h>
  8. #include <time.h>
  9. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  10. #include <hwconfig.h>
  11. #endif
  12. #include <asm/fsl_serdes.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/io.h>
  15. #include <asm/processor.h>
  16. #include <asm/fsl_law.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include "fsl_corenet_serdes.h"
  20. /*
  21. * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
  22. * The code is already very complicated as it is, and separating the two
  23. * completely would just make things worse. We try to keep them as separate
  24. * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
  25. */
  26. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  27. #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
  28. #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
  29. #endif
  30. #endif
  31. static u32 serdes_prtcl_map;
  32. #ifdef DEBUG
  33. static const char *serdes_prtcl_str[] = {
  34. [NONE] = "NA",
  35. [PCIE1] = "PCIE1",
  36. [PCIE2] = "PCIE2",
  37. [PCIE3] = "PCIE3",
  38. [PCIE4] = "PCIE4",
  39. [SATA1] = "SATA1",
  40. [SATA2] = "SATA2",
  41. [SRIO1] = "SRIO1",
  42. [SRIO2] = "SRIO2",
  43. [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  44. [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  45. [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  46. [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  47. [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  48. [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  49. [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  50. [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  51. [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  52. [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
  53. [XAUI_FM1] = "XAUI_FM1",
  54. [XAUI_FM2] = "XAUI_FM2",
  55. [AURORA] = "DEBUG",
  56. };
  57. #endif
  58. static const struct {
  59. int idx;
  60. unsigned int lpd; /* RCW lane powerdown bit */
  61. int bank;
  62. } lanes[SRDS_MAX_LANES] = {
  63. { 0, 152, FSL_SRDS_BANK_1 },
  64. { 1, 153, FSL_SRDS_BANK_1 },
  65. { 2, 154, FSL_SRDS_BANK_1 },
  66. { 3, 155, FSL_SRDS_BANK_1 },
  67. { 4, 156, FSL_SRDS_BANK_1 },
  68. { 5, 157, FSL_SRDS_BANK_1 },
  69. { 6, 158, FSL_SRDS_BANK_1 },
  70. { 7, 159, FSL_SRDS_BANK_1 },
  71. { 8, 160, FSL_SRDS_BANK_1 },
  72. { 9, 161, FSL_SRDS_BANK_1 },
  73. { 16, 162, FSL_SRDS_BANK_2 },
  74. { 17, 163, FSL_SRDS_BANK_2 },
  75. { 18, 164, FSL_SRDS_BANK_2 },
  76. { 19, 165, FSL_SRDS_BANK_2 },
  77. #ifdef CONFIG_ARCH_P4080
  78. { 20, 170, FSL_SRDS_BANK_3 },
  79. { 21, 171, FSL_SRDS_BANK_3 },
  80. { 22, 172, FSL_SRDS_BANK_3 },
  81. { 23, 173, FSL_SRDS_BANK_3 },
  82. #else
  83. { 20, 166, FSL_SRDS_BANK_3 },
  84. { 21, 167, FSL_SRDS_BANK_3 },
  85. { 22, 168, FSL_SRDS_BANK_3 },
  86. { 23, 169, FSL_SRDS_BANK_3 },
  87. #endif
  88. #if SRDS_MAX_BANK > 3
  89. { 24, 175, FSL_SRDS_BANK_4 },
  90. { 25, 176, FSL_SRDS_BANK_4 },
  91. #endif
  92. };
  93. int serdes_get_lane_idx(int lane)
  94. {
  95. return lanes[lane].idx;
  96. }
  97. int serdes_get_bank_by_lane(int lane)
  98. {
  99. return lanes[lane].bank;
  100. }
  101. int serdes_lane_enabled(int lane)
  102. {
  103. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  104. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  105. int bank = lanes[lane].bank;
  106. int word = lanes[lane].lpd / 32;
  107. int bit = lanes[lane].lpd % 32;
  108. if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
  109. return 0;
  110. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  111. /*
  112. * For banks two and three, use the srds_lpd_b[] array instead of the
  113. * RCW, because this array contains the real values of SRDS_LPD_B2 and
  114. * SRDS_LPD_B3.
  115. */
  116. if (bank > 0)
  117. return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
  118. #endif
  119. return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
  120. }
  121. int is_serdes_configured(enum srds_prtcl device)
  122. {
  123. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  124. /* Is serdes enabled at all? */
  125. if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
  126. return 0;
  127. if (!(serdes_prtcl_map & (1 << NONE)))
  128. fsl_serdes_init();
  129. return (1 << device) & serdes_prtcl_map;
  130. }
  131. static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
  132. {
  133. int i;
  134. for (i = 0; i < SRDS_MAX_LANES; i++) {
  135. if (serdes_get_prtcl(prtcl, i) == device)
  136. return i;
  137. }
  138. return -ENODEV;
  139. }
  140. /*
  141. * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
  142. * device. This depends on the current SERDES protocol, as defined in the RCW.
  143. *
  144. * Returns a negative error code if SERDES is disabled or the given device is
  145. * not supported in the current SERDES protocol.
  146. */
  147. int serdes_get_first_lane(enum srds_prtcl device)
  148. {
  149. u32 prtcl;
  150. const ccsr_gur_t *gur;
  151. gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
  152. /* Is serdes enabled at all? */
  153. if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
  154. return -ENODEV;
  155. prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  156. return __serdes_get_first_lane(prtcl, device);
  157. }
  158. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
  159. /*
  160. * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
  161. * SERDES protocol.
  162. *
  163. * Returns a negative error code if the given device is not supported for the
  164. * given SERDES protocol.
  165. */
  166. static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
  167. {
  168. int lane;
  169. lane = __serdes_get_first_lane(prtcl, device);
  170. if (unlikely(lane < 0))
  171. return lane;
  172. return serdes_get_bank_by_lane(lane);
  173. }
  174. static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
  175. int first)
  176. {
  177. int lane;
  178. for (lane = first; lane < SRDS_MAX_LANES; lane++) {
  179. if (serdes_get_prtcl(prtcl, lane) != device)
  180. break;
  181. }
  182. return lane - first;
  183. }
  184. static void __serdes_reset_rx(serdes_corenet_t *regs,
  185. uint32_t prtcl,
  186. enum srds_prtcl device)
  187. {
  188. int lane, idx, first, last;
  189. lane = __serdes_get_first_lane(prtcl, device);
  190. if (unlikely(lane < 0))
  191. return;
  192. first = serdes_get_lane_idx(lane);
  193. last = first + __serdes_get_lane_count(prtcl, device, lane);
  194. /*
  195. * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
  196. * selected as XAUI to place the lane into reset.
  197. */
  198. for (idx = first; idx < last; idx++)
  199. clrbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
  200. /* Wait at least 250 ns */
  201. udelay(1);
  202. /*
  203. * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
  204. * selected as XAUI to bring the lane out of reset.
  205. */
  206. for (idx = first; idx < last; idx++)
  207. setbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
  208. }
  209. void serdes_reset_rx(enum srds_prtcl device)
  210. {
  211. u32 prtcl;
  212. const ccsr_gur_t *gur;
  213. serdes_corenet_t *regs;
  214. if (unlikely(device == NONE))
  215. return;
  216. gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
  217. /* Is serdes enabled at all? */
  218. if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
  219. return;
  220. regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  221. prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  222. __serdes_reset_rx(regs, prtcl, device);
  223. }
  224. #endif
  225. #ifndef CONFIG_SYS_DCSRBAR_PHYS
  226. #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
  227. #define CONFIG_SYS_DCSRBAR 0x80000000
  228. #define __DCSR_NOT_DEFINED_BY_CONFIG
  229. #endif
  230. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  231. /*
  232. * Enable a SERDES bank that was disabled via the RCW
  233. *
  234. * We only call this function for SERDES8 and SERDES-A001 in cases we really
  235. * want to enable the bank, whether we actually want to use the lanes or not,
  236. * so make sure at least one lane is enabled. We're only enabling this one
  237. * lane to satisfy errata requirements that the bank be enabled.
  238. *
  239. * We use a local variable instead of srds_lpd_b[] because we want drivers to
  240. * think that the lanes actually are disabled.
  241. */
  242. static void enable_bank(ccsr_gur_t *gur, int bank)
  243. {
  244. u32 rcw5;
  245. u32 temp_lpd_b = srds_lpd_b[bank];
  246. /*
  247. * If we're asked to disable all lanes, just pretend we're doing
  248. * that.
  249. */
  250. if (temp_lpd_b == 0xF)
  251. temp_lpd_b = 0xE;
  252. /*
  253. * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
  254. * CCSR, and read/write in DSCR.
  255. */
  256. rcw5 = in_be32(gur->rcwsr + 5);
  257. if (bank == FSL_SRDS_BANK_2) {
  258. rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
  259. rcw5 |= temp_lpd_b << 26;
  260. } else if (bank == FSL_SRDS_BANK_3) {
  261. rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
  262. rcw5 |= temp_lpd_b << 18;
  263. } else {
  264. printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
  265. return;
  266. }
  267. /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
  268. * of the DCSR mapping.
  269. */
  270. {
  271. #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
  272. struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
  273. int law_index;
  274. if (law.index == -1)
  275. law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
  276. LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
  277. else
  278. set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
  279. LAW_TRGT_IF_DCSR);
  280. #endif
  281. u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
  282. out_be32(p, rcw5);
  283. #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
  284. if (law.index == -1)
  285. disable_law(law_index);
  286. else
  287. set_law(law.index, law.addr, law.size, law.trgt_id);
  288. #endif
  289. }
  290. }
  291. /*
  292. * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
  293. * bank 3 to clock banks 2 and 3, as well as a limited selection of
  294. * protocol configurations. This requires that banks 2 and 3's lanes be
  295. * disabled in the RCW, and enabled with some fixup here to re-enable
  296. * them, and to configure bank 2's clock parameters in bank 3's pll in
  297. * cases where they differ.
  298. */
  299. static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
  300. u32 devdisr, u32 devdisr2, int cfg)
  301. {
  302. int srds_ratio_b2;
  303. int rfck_sel;
  304. /*
  305. * The disabled lanes of bank 2 will cause the associated
  306. * logic blocks to be disabled in DEVDISR. We reverse that here.
  307. *
  308. * Note that normally it is not permitted to clear DEVDISR bits
  309. * once the device has been disabled, but the hardware people
  310. * say that this special case is OK.
  311. */
  312. clrbits_be32(&gur->devdisr, devdisr);
  313. clrbits_be32(&gur->devdisr2, devdisr2);
  314. /*
  315. * Some protocols require special handling. There are a few
  316. * additional protocol configurations that can be used, which are
  317. * not listed here. See app note 4065 for supported protocol
  318. * configurations.
  319. */
  320. switch (cfg) {
  321. case 0x19:
  322. /*
  323. * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
  324. * SGMII on bank 3 should still be usable.
  325. */
  326. setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
  327. SRDS_PLLCR1_PLL_BWSEL);
  328. break;
  329. case 0x0f:
  330. case 0x10:
  331. /*
  332. * Banks 2 (XAUI) and 3 (SGMII) have different clocking
  333. * requirements in these configurations. Bank 3 cannot
  334. * be used and should have its lanes (but not the bank
  335. * itself) disabled in the RCW. We set up bank 3's pll
  336. * for bank 2's needs here.
  337. */
  338. srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
  339. /* Determine refclock from XAUI ratio */
  340. switch (srds_ratio_b2) {
  341. case 1: /* 20:1 */
  342. rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
  343. break;
  344. case 2: /* 25:1 */
  345. rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
  346. break;
  347. default:
  348. printf("SERDES: bad SRDS_RATIO_B2 %d\n",
  349. srds_ratio_b2);
  350. return;
  351. }
  352. clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
  353. SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
  354. clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
  355. SRDS_PLLCR0_FRATE_SEL_MASK,
  356. SRDS_PLLCR0_FRATE_SEL_6_25);
  357. break;
  358. }
  359. enable_bank(gur, FSL_SRDS_BANK_3);
  360. }
  361. #endif
  362. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  363. /*
  364. * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
  365. * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
  366. */
  367. static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
  368. {
  369. enum srds_prtcl device;
  370. switch (cfg) {
  371. case 0x13:
  372. case 0x16:
  373. /*
  374. * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
  375. * to 0.
  376. */
  377. clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
  378. SRDS_PLLCR1_PLL_BWSEL);
  379. break;
  380. case 0x19:
  381. /*
  382. * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
  383. * SRDSB3PLLCR1[PLLBW_SEL] to 1.
  384. */
  385. clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
  386. SRDS_PLLCR1_PLL_BWSEL);
  387. setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
  388. SRDS_PLLCR1_PLL_BWSEL);
  389. break;
  390. }
  391. /*
  392. * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
  393. * before XAUI is initialized.
  394. */
  395. for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
  396. if (is_serdes_configured(device)) {
  397. int bank = serdes_get_bank_by_device(cfg, device);
  398. clrbits_be32(&regs->bank[bank].pllcr1,
  399. SRDS_PLLCR1_PLL_BWSEL);
  400. }
  401. }
  402. }
  403. #endif
  404. /*
  405. * Wait for the RSTDONE bit to get set, or a one-second timeout.
  406. */
  407. static void wait_for_rstdone(unsigned int bank)
  408. {
  409. serdes_corenet_t *srds_regs =
  410. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  411. unsigned long long end_tick;
  412. u32 rstctl;
  413. /* wait for reset complete or 1-second timeout */
  414. end_tick = usec2ticks(1000000) + get_ticks();
  415. do {
  416. rstctl = in_be32(&srds_regs->bank[bank].rstctl);
  417. if (rstctl & SRDS_RSTCTL_RSTDONE)
  418. break;
  419. } while (end_tick > get_ticks());
  420. if (!(rstctl & SRDS_RSTCTL_RSTDONE))
  421. printf("SERDES: timeout resetting bank %u\n", bank + 1);
  422. }
  423. static void __soc_serdes_init(void)
  424. {
  425. /* Allow for SoC-specific initialization in <SOC>_serdes.c */
  426. };
  427. void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
  428. void fsl_serdes_init(void)
  429. {
  430. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  431. int cfg;
  432. serdes_corenet_t *srds_regs;
  433. #ifdef CONFIG_ARCH_P5040
  434. serdes_corenet_t *srds2_regs;
  435. #endif
  436. int lane, bank, idx;
  437. int have_bank[SRDS_MAX_BANK] = {};
  438. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  439. u32 serdes8_devdisr = 0;
  440. u32 serdes8_devdisr2 = 0;
  441. char srds_lpd_opt[16];
  442. const char *srds_lpd_arg;
  443. size_t arglen;
  444. #endif
  445. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  446. int need_serdes_a001; /* true == need work-around for SERDES A001 */
  447. #endif
  448. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  449. char buffer[HWCONFIG_BUFFER_SIZE];
  450. char *buf = NULL;
  451. /*
  452. * Extract hwconfig from environment since we have not properly setup
  453. * the environment but need it for ddr config params
  454. */
  455. if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
  456. buf = buffer;
  457. #endif
  458. if (serdes_prtcl_map & (1 << NONE))
  459. return;
  460. /* Is serdes enabled at all? */
  461. if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
  462. return;
  463. srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
  464. cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  465. debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
  466. if (!is_serdes_prtcl_valid(cfg)) {
  467. printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
  468. return;
  469. }
  470. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  471. /*
  472. * Display a warning if banks two and three are not disabled in the RCW,
  473. * since our work-around for SERDES8 depends on these banks being
  474. * disabled at power-on.
  475. */
  476. #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
  477. if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
  478. printf("Warning: SERDES8 requires banks two and "
  479. "three to be disabled in the RCW\n");
  480. }
  481. /*
  482. * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
  483. * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
  484. * for a description of these options.
  485. */
  486. for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
  487. sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
  488. srds_lpd_arg =
  489. hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
  490. if (srds_lpd_arg)
  491. srds_lpd_b[bank] =
  492. simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
  493. }
  494. if ((cfg == 0xf) || (cfg == 0x10)) {
  495. /*
  496. * For SERDES protocols 0xF and 0x10, force bank 3 to be
  497. * disabled, because it is not supported.
  498. */
  499. srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
  500. }
  501. #endif
  502. /* Look for banks with all lanes disabled, and power down the bank. */
  503. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  504. enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
  505. if (serdes_lane_enabled(lane)) {
  506. have_bank[serdes_get_bank_by_lane(lane)] = 1;
  507. serdes_prtcl_map |= (1 << lane_prtcl);
  508. }
  509. }
  510. #ifdef CONFIG_ARCH_P5040
  511. /*
  512. * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
  513. * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
  514. * to decide whether a protocol is supported on a given lane, so SATA
  515. * will be identified as not supported, and therefore not initialized.
  516. * So for protocols which use SATA on bank4, we add SATA support in
  517. * serdes_prtcl_map.
  518. */
  519. switch (cfg) {
  520. case 0x0:
  521. case 0x1:
  522. case 0x2:
  523. case 0x3:
  524. case 0x4:
  525. case 0x5:
  526. case 0x6:
  527. case 0x7:
  528. serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
  529. break;
  530. default:
  531. srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
  532. /* We don't need bank 4, so power it down */
  533. setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
  534. }
  535. #endif
  536. soc_serdes_init();
  537. /* Set the first bit to indicate serdes has been initialized */
  538. serdes_prtcl_map |= (1 << NONE);
  539. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  540. /*
  541. * Bank two uses the clock from bank three, so if bank two is enabled,
  542. * then bank three must also be enabled.
  543. */
  544. if (have_bank[FSL_SRDS_BANK_2])
  545. have_bank[FSL_SRDS_BANK_3] = 1;
  546. #endif
  547. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  548. /*
  549. * The work-aroud for erratum SERDES-A001 is needed only if bank two
  550. * is disabled and bank three is enabled. The converse is also true,
  551. * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
  552. * enabled, so there's no point in complicating the code to handle
  553. * that situation.
  554. */
  555. need_serdes_a001 =
  556. !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
  557. #endif
  558. /* Power down the banks we're not interested in */
  559. for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
  560. if (!have_bank[bank]) {
  561. printf("SERDES: bank %d disabled\n", bank + 1);
  562. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  563. /*
  564. * Erratum SERDES-A001 says bank two needs to be powered
  565. * down after bank three is powered up, so don't power
  566. * down bank two here.
  567. */
  568. if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
  569. setbits_be32(&srds_regs->bank[bank].rstctl,
  570. SRDS_RSTCTL_SDPD);
  571. #else
  572. setbits_be32(&srds_regs->bank[bank].rstctl,
  573. SRDS_RSTCTL_SDPD);
  574. #endif
  575. }
  576. }
  577. #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
  578. /*
  579. * To avoid the situation that resulted in the P4080 erratum
  580. * SERDES-8, a given SerDes bank will use the PLLs from the previous
  581. * bank if one of the PLL frequencies is a multiple of the other. For
  582. * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
  583. * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
  584. * that, in this situation, lane synchronization is not initiated. So
  585. * when we detect a bank with a "borrowed" PLL, we have to manually
  586. * initiate lane synchronization.
  587. */
  588. for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
  589. /* Determine the first lane for this bank */
  590. unsigned int lane;
  591. for (lane = 0; lane < SRDS_MAX_LANES; lane++)
  592. if (lanes[lane].bank == bank)
  593. break;
  594. idx = lanes[lane].idx;
  595. /*
  596. * Check if the PLL for the bank is borrowed. The UOTHL
  597. * bit of the first lane will tell us that.
  598. */
  599. if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
  600. /* Manually start lane synchronization */
  601. setbits_be32(&srds_regs->bank[bank].pllcr0,
  602. SRDS_PLLCR0_PVCOCNT_EN);
  603. }
  604. }
  605. #endif
  606. #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
  607. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  608. enum srds_prtcl lane_prtcl;
  609. idx = serdes_get_lane_idx(lane);
  610. lane_prtcl = serdes_get_prtcl(cfg, lane);
  611. #ifdef DEBUG
  612. switch (lane) {
  613. case 0:
  614. puts("Bank1: ");
  615. break;
  616. case 10:
  617. puts("\nBank2: ");
  618. break;
  619. case 14:
  620. puts("\nBank3: ");
  621. break;
  622. default:
  623. break;
  624. }
  625. printf("%s ", serdes_prtcl_str[lane_prtcl]);
  626. #endif
  627. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
  628. /*
  629. * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
  630. * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
  631. * or AURORA before the device is initialized.
  632. *
  633. * Note that this part of the SERDES-9 work-around is
  634. * redundant if the work-around for A-4580 has already been
  635. * applied via PBI.
  636. */
  637. switch (lane_prtcl) {
  638. case SGMII_FM1_DTSEC1:
  639. case SGMII_FM1_DTSEC2:
  640. case SGMII_FM1_DTSEC3:
  641. case SGMII_FM1_DTSEC4:
  642. case SGMII_FM2_DTSEC1:
  643. case SGMII_FM2_DTSEC2:
  644. case SGMII_FM2_DTSEC3:
  645. case SGMII_FM2_DTSEC4:
  646. case SGMII_FM2_DTSEC5:
  647. case XAUI_FM1:
  648. case XAUI_FM2:
  649. case SRIO1:
  650. case SRIO2:
  651. case AURORA:
  652. out_be32(&srds_regs->lane[idx].ttlcr0,
  653. SRDS_TTLCR0_FLT_SEL_KFR_26 |
  654. SRDS_TTLCR0_FLT_SEL_KPH_28 |
  655. SRDS_TTLCR0_FLT_SEL_750PPM |
  656. SRDS_TTLCR0_FREQOVD_EN);
  657. break;
  658. default:
  659. break;
  660. }
  661. #endif
  662. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  663. switch (lane_prtcl) {
  664. case PCIE1:
  665. case PCIE2:
  666. case PCIE3:
  667. serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
  668. (lane_prtcl - PCIE1);
  669. break;
  670. case SRIO1:
  671. case SRIO2:
  672. serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
  673. (lane_prtcl - SRIO1);
  674. break;
  675. case SGMII_FM1_DTSEC1:
  676. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
  677. FSL_CORENET_DEVDISR2_DTSEC1_1;
  678. break;
  679. case SGMII_FM1_DTSEC2:
  680. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
  681. FSL_CORENET_DEVDISR2_DTSEC1_2;
  682. break;
  683. case SGMII_FM1_DTSEC3:
  684. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
  685. FSL_CORENET_DEVDISR2_DTSEC1_3;
  686. break;
  687. case SGMII_FM1_DTSEC4:
  688. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
  689. FSL_CORENET_DEVDISR2_DTSEC1_4;
  690. break;
  691. case SGMII_FM2_DTSEC1:
  692. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  693. FSL_CORENET_DEVDISR2_DTSEC2_1;
  694. break;
  695. case SGMII_FM2_DTSEC2:
  696. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  697. FSL_CORENET_DEVDISR2_DTSEC2_2;
  698. break;
  699. case SGMII_FM2_DTSEC3:
  700. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  701. FSL_CORENET_DEVDISR2_DTSEC2_3;
  702. break;
  703. case SGMII_FM2_DTSEC4:
  704. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  705. FSL_CORENET_DEVDISR2_DTSEC2_4;
  706. break;
  707. case SGMII_FM2_DTSEC5:
  708. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  709. FSL_CORENET_DEVDISR2_DTSEC2_5;
  710. break;
  711. case XAUI_FM1:
  712. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
  713. FSL_CORENET_DEVDISR2_10GEC1;
  714. break;
  715. case XAUI_FM2:
  716. serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
  717. FSL_CORENET_DEVDISR2_10GEC2;
  718. break;
  719. case AURORA:
  720. break;
  721. default:
  722. break;
  723. }
  724. #endif
  725. }
  726. #endif
  727. #ifdef DEBUG
  728. puts("\n");
  729. #endif
  730. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  731. p4080_erratum_serdes_a005(srds_regs, cfg);
  732. #endif
  733. for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
  734. bank = idx;
  735. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  736. /*
  737. * Change bank init order to 0, 2, 1, so that the third bank's
  738. * PLL is established before we start the second bank. The
  739. * second bank uses the third bank's PLL.
  740. */
  741. if (idx == 1)
  742. bank = FSL_SRDS_BANK_3;
  743. else if (idx == 2)
  744. bank = FSL_SRDS_BANK_2;
  745. #endif
  746. /* Skip disabled banks */
  747. if (!have_bank[bank])
  748. continue;
  749. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  750. if (idx == 1) {
  751. /*
  752. * Re-enable devices on banks two and three that were
  753. * disabled by the RCW, and then enable bank three. The
  754. * devices need to be enabled before either bank is
  755. * powered up.
  756. */
  757. p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
  758. serdes8_devdisr2, cfg);
  759. } else if (idx == 2) {
  760. /* Enable bank two now that bank three is enabled. */
  761. enable_bank(gur, FSL_SRDS_BANK_2);
  762. }
  763. #endif
  764. wait_for_rstdone(bank);
  765. }
  766. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  767. if (need_serdes_a001) {
  768. /* Bank 3 has been enabled, so now we can disable bank 2 */
  769. setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
  770. SRDS_RSTCTL_SDPD);
  771. }
  772. #endif
  773. }
  774. const char *serdes_clock_to_string(u32 clock)
  775. {
  776. switch (clock) {
  777. case SRDS_PLLCR0_RFCK_SEL_100:
  778. return "100";
  779. case SRDS_PLLCR0_RFCK_SEL_125:
  780. return "125";
  781. case SRDS_PLLCR0_RFCK_SEL_156_25:
  782. return "156.25";
  783. case SRDS_PLLCR0_RFCK_SEL_161_13:
  784. return "161.1328123";
  785. default:
  786. return "150";
  787. }
  788. }