fsl_corenet2_serdes.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/fsl_serdes.h>
  8. #include <asm/immap_85xx.h>
  9. #include <asm/io.h>
  10. #include <asm/processor.h>
  11. #include <asm/fsl_law.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <fsl_errata.h>
  15. #include "fsl_corenet2_serdes.h"
  16. #ifdef CONFIG_SYS_FSL_SRDS_1
  17. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  18. #endif
  19. #ifdef CONFIG_SYS_FSL_SRDS_2
  20. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  21. #endif
  22. #ifdef CONFIG_SYS_FSL_SRDS_3
  23. static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  24. #endif
  25. #ifdef CONFIG_SYS_FSL_SRDS_4
  26. static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
  27. #endif
  28. #ifdef DEBUG
  29. static const char *serdes_prtcl_str[] = {
  30. [NONE] = "NA",
  31. [PCIE1] = "PCIE1",
  32. [PCIE2] = "PCIE2",
  33. [PCIE3] = "PCIE3",
  34. [PCIE4] = "PCIE4",
  35. [SATA1] = "SATA1",
  36. [SATA2] = "SATA2",
  37. [SRIO1] = "SRIO1",
  38. [SRIO2] = "SRIO2",
  39. [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  40. [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  41. [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  42. [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  43. [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  44. [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
  45. [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  46. [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  47. [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  48. [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  49. [XAUI_FM1] = "XAUI_FM1",
  50. [XAUI_FM2] = "XAUI_FM2",
  51. [AURORA] = "DEBUG",
  52. [CPRI1] = "CPRI1",
  53. [CPRI2] = "CPRI2",
  54. [CPRI3] = "CPRI3",
  55. [CPRI4] = "CPRI4",
  56. [CPRI5] = "CPRI5",
  57. [CPRI6] = "CPRI6",
  58. [CPRI7] = "CPRI7",
  59. [CPRI8] = "CPRI8",
  60. [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
  61. [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
  62. [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
  63. [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
  64. [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
  65. [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
  66. [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
  67. [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
  68. [QSGMII_FM1_A] = "QSGMII_FM1_A",
  69. [QSGMII_FM1_B] = "QSGMII_FM1_B",
  70. [QSGMII_FM2_A] = "QSGMII_FM2_A",
  71. [QSGMII_FM2_B] = "QSGMII_FM2_B",
  72. [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
  73. [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
  74. [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
  75. [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
  76. [INTERLAKEN] = "INTERLAKEN",
  77. [QSGMII_SW1_A] = "QSGMII_SW1_A",
  78. [QSGMII_SW1_B] = "QSGMII_SW1_B",
  79. [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
  80. [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
  81. [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
  82. [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
  83. [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
  84. [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
  85. };
  86. #endif
  87. int is_serdes_configured(enum srds_prtcl device)
  88. {
  89. int ret = 0;
  90. #ifdef CONFIG_SYS_FSL_SRDS_1
  91. if (!serdes1_prtcl_map[NONE])
  92. fsl_serdes_init();
  93. ret |= serdes1_prtcl_map[device];
  94. #endif
  95. #ifdef CONFIG_SYS_FSL_SRDS_2
  96. if (!serdes2_prtcl_map[NONE])
  97. fsl_serdes_init();
  98. ret |= serdes2_prtcl_map[device];
  99. #endif
  100. #ifdef CONFIG_SYS_FSL_SRDS_3
  101. if (!serdes3_prtcl_map[NONE])
  102. fsl_serdes_init();
  103. ret |= serdes3_prtcl_map[device];
  104. #endif
  105. #ifdef CONFIG_SYS_FSL_SRDS_4
  106. if (!serdes4_prtcl_map[NONE])
  107. fsl_serdes_init();
  108. ret |= serdes4_prtcl_map[device];
  109. #endif
  110. return !!ret;
  111. }
  112. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  113. {
  114. const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  115. u32 cfg = in_be32(&gur->rcwsr[4]);
  116. int i;
  117. switch (sd) {
  118. #ifdef CONFIG_SYS_FSL_SRDS_1
  119. case FSL_SRDS_1:
  120. cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  121. cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  122. break;
  123. #endif
  124. #ifdef CONFIG_SYS_FSL_SRDS_2
  125. case FSL_SRDS_2:
  126. cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  127. cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  128. break;
  129. #endif
  130. #ifdef CONFIG_SYS_FSL_SRDS_3
  131. case FSL_SRDS_3:
  132. cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
  133. cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
  134. break;
  135. #endif
  136. #ifdef CONFIG_SYS_FSL_SRDS_4
  137. case FSL_SRDS_4:
  138. cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  139. cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  140. break;
  141. #endif
  142. default:
  143. printf("invalid SerDes%d\n", sd);
  144. break;
  145. }
  146. /* Is serdes enabled at all? */
  147. if (unlikely(cfg == 0))
  148. return -ENODEV;
  149. for (i = 0; i < SRDS_MAX_LANES; i++) {
  150. if (serdes_get_prtcl(sd, cfg, i) == device)
  151. return i;
  152. }
  153. return -ENODEV;
  154. }
  155. #define BC3_SHIFT 9
  156. #define DC3_SHIFT 6
  157. #define FC3_SHIFT 0
  158. #define BC2_SHIFT 19
  159. #define DC2_SHIFT 16
  160. #define FC2_SHIFT 10
  161. #define BC1_SHIFT 29
  162. #define DC1_SHIFT 26
  163. #define FC1_SHIFT 20
  164. #define BC_MASK 0x1
  165. #define DC_MASK 0x7
  166. #define FC_MASK 0x3F
  167. #define FUSE_VAL_MASK 0x00000003
  168. #define FUSE_VAL_SHIFT 30
  169. #define CR0_DCBIAS_SHIFT 5
  170. #define CR1_FCAP_SHIFT 15
  171. #define CR1_BCAP_SHIFT 29
  172. #define FCAP_MASK 0x001F8000
  173. #define BCAP_MASK 0x20000000
  174. #define BCAP_OVD_MASK 0x10000000
  175. #define BYP_CAL_MASK 0x02000000
  176. void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
  177. u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  178. {
  179. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  180. u32 cfg;
  181. int lane;
  182. if (serdes_prtcl_map[NONE])
  183. return;
  184. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  185. #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
  186. struct ccsr_sfp_regs __iomem *sfp_regs =
  187. (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
  188. u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
  189. u32 bc_status, fc_status, dc_status, pll_sr2;
  190. serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
  191. u32 sfp_spfr0, sel;
  192. #endif
  193. cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
  194. /* Erratum A-007186
  195. * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
  196. * The workaround requires factory pre-set SerDes calibration values to be
  197. * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
  198. * These values have been shown to work across the
  199. * entire temperature range for all SerDes. These values are then written into
  200. * the SerDes registers to calibrate the SerDes PLL.
  201. *
  202. * This workaround for the protocols and rates that only have the Ring VCO.
  203. */
  204. #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
  205. sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
  206. debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
  207. sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
  208. if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
  209. for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
  210. pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
  211. debug("A007186: pll_num=%x pllcr0=%x\n",
  212. pll_num, pll_status);
  213. /* STEP 1 */
  214. /* Read factory pre-set SerDes calibration values
  215. * from fuse block(SFP scratch register-sfp_spfr0)
  216. */
  217. switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
  218. case SRDS_PLLCR0_FRATE_SEL_3_0:
  219. case SRDS_PLLCR0_FRATE_SEL_3_072:
  220. debug("A007186: 3.0/3.072 protocol rate\n");
  221. bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
  222. dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
  223. fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
  224. break;
  225. case SRDS_PLLCR0_FRATE_SEL_3_125:
  226. debug("A007186: 3.125 protocol rate\n");
  227. bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
  228. dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
  229. fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
  230. break;
  231. case SRDS_PLLCR0_FRATE_SEL_3_75:
  232. debug("A007186: 3.75 protocol rate\n");
  233. bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
  234. dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
  235. fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
  236. break;
  237. default:
  238. continue;
  239. }
  240. /* STEP 2 */
  241. /* Write SRDSxPLLnCR1[11:16] = FC
  242. * Write SRDSxPLLnCR1[2] = BC
  243. */
  244. pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
  245. pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
  246. ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
  247. out_be32(&srds_regs->bank[pll_num].pllcr1,
  248. (pll_cr_upd | pll_cr1));
  249. debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
  250. pll_num, (pll_cr_upd | pll_cr1));
  251. /* Write SRDSxPLLnCR0[24:26] = DC
  252. */
  253. pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
  254. out_be32(&srds_regs->bank[pll_num].pllcr0,
  255. pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
  256. debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
  257. pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
  258. /* Write SRDSxPLLnCR1[3] = 1
  259. * Write SRDSxPLLnCR1[6] = 1
  260. */
  261. pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
  262. pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
  263. out_be32(&srds_regs->bank[pll_num].pllcr1,
  264. (pll_cr_upd | pll_cr1));
  265. debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
  266. pll_num, (pll_cr_upd | pll_cr1));
  267. /* STEP 3 */
  268. /* Read the status Registers */
  269. /* Verify SRDSxPLLnSR2[8] = BC */
  270. pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
  271. debug("A007186: pll_num=%x pllsr2=%x\n",
  272. pll_num, pll_sr2);
  273. bc_status = (pll_sr2 >> 23) & BC_MASK;
  274. if (bc_status != bc)
  275. debug("BC mismatch\n");
  276. fc_status = (pll_sr2 >> 16) & FC_MASK;
  277. if (fc_status != fc)
  278. debug("FC mismatch\n");
  279. pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
  280. out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
  281. 0x02000000);
  282. pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
  283. dc_status = (pll_sr2 >> 17) & DC_MASK;
  284. if (dc_status != dc)
  285. debug("DC mismatch\n");
  286. pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
  287. out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
  288. 0xfdffffff);
  289. /* STEP 4 */
  290. /* Wait 750us to verify the PLL is locked
  291. * by checking SRDSxPLLnCR0[8] = 1.
  292. */
  293. udelay(750);
  294. pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
  295. debug("A007186: pll_num=%x pllcr0=%x\n",
  296. pll_num, pll_status);
  297. if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
  298. printf("A007186 Serdes PLL not locked\n");
  299. else
  300. debug("A007186 Serdes PLL locked\n");
  301. }
  302. }
  303. #endif
  304. cfg >>= sd_prctl_shift;
  305. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  306. if (!is_serdes_prtcl_valid(sd, cfg))
  307. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  308. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  309. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  310. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  311. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  312. else
  313. serdes_prtcl_map[lane_prtcl] = 1;
  314. }
  315. /* Set the first element to indicate serdes has been initialized */
  316. serdes_prtcl_map[NONE] = 1;
  317. }
  318. void fsl_serdes_init(void)
  319. {
  320. #ifdef CONFIG_SYS_FSL_SRDS_1
  321. serdes_init(FSL_SRDS_1,
  322. CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
  323. FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
  324. FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
  325. serdes1_prtcl_map);
  326. #endif
  327. #ifdef CONFIG_SYS_FSL_SRDS_2
  328. serdes_init(FSL_SRDS_2,
  329. CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
  330. FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
  331. FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
  332. serdes2_prtcl_map);
  333. #endif
  334. #ifdef CONFIG_SYS_FSL_SRDS_3
  335. serdes_init(FSL_SRDS_3,
  336. CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
  337. FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
  338. FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
  339. serdes3_prtcl_map);
  340. #endif
  341. #ifdef CONFIG_SYS_FSL_SRDS_4
  342. serdes_init(FSL_SRDS_4,
  343. CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
  344. FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
  345. FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
  346. serdes4_prtcl_map);
  347. #endif
  348. }
  349. const char *serdes_clock_to_string(u32 clock)
  350. {
  351. switch (clock) {
  352. case SRDS_PLLCR0_RFCK_SEL_100:
  353. return "100";
  354. case SRDS_PLLCR0_RFCK_SEL_125:
  355. return "125";
  356. case SRDS_PLLCR0_RFCK_SEL_156_25:
  357. return "156.25";
  358. case SRDS_PLLCR0_RFCK_SEL_161_13:
  359. return "161.1328123";
  360. default:
  361. #if defined(CONFIG_TARGET_T4240QDS)
  362. return "???";
  363. #else
  364. return "122.88";
  365. #endif
  366. }
  367. }