m5307.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
  4. *
  5. */
  6. #ifndef mcf5307_h
  7. #define mcf5307_h
  8. /*
  9. * Size of internal RAM (RAMBAR)
  10. */
  11. #define INT_RAM_SIZE 4096
  12. /* Bit definitions and macros for SYPCR */
  13. #define SYPCR_SWTAVAL 0x02
  14. #define SYPCR_SWTA 0x04
  15. #define SYPCR_SWT(x) ((x&0x3)<<3)
  16. #define SYPCR_SWP 0x20
  17. #define SYPCR_SWRI 0x40
  18. #define SYPCR_SWE 0x80
  19. /* Bit definitions and macros for CSMR */
  20. #define CSMR_V 0x01
  21. #define CSMR_UD 0x02
  22. #define CSMR_UC 0x04
  23. #define CSMR_SD 0x08
  24. #define CSMR_SC 0x10
  25. #define CSMR_CI 0x20
  26. #define CSMR_AM 0x40
  27. #define CSMR_WP 0x100
  28. /* Bit definitions and macros for DACR (SDRAM) */
  29. #define DACR_PM_CONTINUOUS 0x04
  30. #define DACR_IP_PRECHG_ALL 0x08
  31. #define DACR_PORT_SZ_32 0
  32. #define DACR_PORT_SZ_8 (1<<4)
  33. #define DACR_PORT_SZ_16 (2<<4)
  34. #define DACR_IMRS_INIT_CMD (1<<6)
  35. #define DACR_CMD_PIN(x) ((x&7)<<8)
  36. #define DACR_CASL(x) ((x&3)<<12)
  37. #define DACR_RE (1<<15)
  38. /* Bit definitions and macros for CSCR */
  39. #define CSCR_BSTW 0x08
  40. #define CSCR_BSTR 0x10
  41. #define CSCR_BEM 0x20
  42. #define CSCR_PS(x) ((x&0x3)<<6)
  43. #define CSCR_AA 0x100
  44. #define CSCR_WS ((x&0xf)<<10)
  45. /* Bit definitions for the ICR family of registers */
  46. #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
  47. #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
  48. #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
  49. #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
  50. #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
  51. #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
  52. #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
  53. #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
  54. #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
  55. #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
  56. #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
  57. #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
  58. #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
  59. #endif /* mcf5307_h */