vf610_nfc.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
  4. *
  5. * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
  6. * Ported to U-Boot by Stefan Agner
  7. * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
  8. * Jason ported to M54418TWR and MVFA5.
  9. * Authors: Stefan Agner <stefan.agner@toradex.com>
  10. * Bill Pringlemeir <bpringlemeir@nbsps.com>
  11. * Shaohui Xie <b21989@freescale.com>
  12. * Jason Jin <Jason.jin@freescale.com>
  13. *
  14. * Based on original driver mpc5121_nfc.c.
  15. *
  16. * Limitations:
  17. * - Untested on MPC5125 and M54418.
  18. * - DMA and pipelining not used.
  19. * - 2K pages or less.
  20. * - HW ECC: Only 2K page with 64+ OOB.
  21. * - HW ECC: Only 24 and 32-bit error correction implemented.
  22. */
  23. #include <common.h>
  24. #include <malloc.h>
  25. #include <dm/device_compat.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/rawnand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <nand.h>
  30. #include <errno.h>
  31. #include <asm/io.h>
  32. #if CONFIG_NAND_VF610_NFC_DT
  33. #include <dm.h>
  34. #include <linux/io.h>
  35. #include <linux/ioport.h>
  36. #endif
  37. /* Register Offsets */
  38. #define NFC_FLASH_CMD1 0x3F00
  39. #define NFC_FLASH_CMD2 0x3F04
  40. #define NFC_COL_ADDR 0x3F08
  41. #define NFC_ROW_ADDR 0x3F0c
  42. #define NFC_ROW_ADDR_INC 0x3F14
  43. #define NFC_FLASH_STATUS1 0x3F18
  44. #define NFC_FLASH_STATUS2 0x3F1c
  45. #define NFC_CACHE_SWAP 0x3F28
  46. #define NFC_SECTOR_SIZE 0x3F2c
  47. #define NFC_FLASH_CONFIG 0x3F30
  48. #define NFC_IRQ_STATUS 0x3F38
  49. /* Addresses for NFC MAIN RAM BUFFER areas */
  50. #define NFC_MAIN_AREA(n) ((n) * 0x1000)
  51. #define PAGE_2K 0x0800
  52. #define OOB_64 0x0040
  53. #define OOB_MAX 0x0100
  54. /*
  55. * NFC_CMD2[CODE] values. See section:
  56. * - 31.4.7 Flash Command Code Description, Vybrid manual
  57. * - 23.8.6 Flash Command Sequencer, MPC5125 manual
  58. *
  59. * Briefly these are bitmasks of controller cycles.
  60. */
  61. #define READ_PAGE_CMD_CODE 0x7EE0
  62. #define READ_ONFI_PARAM_CMD_CODE 0x4860
  63. #define PROGRAM_PAGE_CMD_CODE 0x7FC0
  64. #define ERASE_CMD_CODE 0x4EC0
  65. #define READ_ID_CMD_CODE 0x4804
  66. #define RESET_CMD_CODE 0x4040
  67. #define STATUS_READ_CMD_CODE 0x4068
  68. /* NFC ECC mode define */
  69. #define ECC_BYPASS 0
  70. #define ECC_45_BYTE 6
  71. #define ECC_60_BYTE 7
  72. /*** Register Mask and bit definitions */
  73. /* NFC_FLASH_CMD1 Field */
  74. #define CMD_BYTE2_MASK 0xFF000000
  75. #define CMD_BYTE2_SHIFT 24
  76. /* NFC_FLASH_CM2 Field */
  77. #define CMD_BYTE1_MASK 0xFF000000
  78. #define CMD_BYTE1_SHIFT 24
  79. #define CMD_CODE_MASK 0x00FFFF00
  80. #define CMD_CODE_SHIFT 8
  81. #define BUFNO_MASK 0x00000006
  82. #define BUFNO_SHIFT 1
  83. #define START_BIT (1<<0)
  84. /* NFC_COL_ADDR Field */
  85. #define COL_ADDR_MASK 0x0000FFFF
  86. #define COL_ADDR_SHIFT 0
  87. /* NFC_ROW_ADDR Field */
  88. #define ROW_ADDR_MASK 0x00FFFFFF
  89. #define ROW_ADDR_SHIFT 0
  90. #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
  91. #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
  92. #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
  93. #define ROW_ADDR_CHIP_SEL_SHIFT 24
  94. /* NFC_FLASH_STATUS2 Field */
  95. #define STATUS_BYTE1_MASK 0x000000FF
  96. /* NFC_FLASH_CONFIG Field */
  97. #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
  98. #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
  99. #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
  100. #define CONFIG_DMA_REQ_BIT (1<<20)
  101. #define CONFIG_ECC_MODE_MASK 0x000E0000
  102. #define CONFIG_ECC_MODE_SHIFT 17
  103. #define CONFIG_FAST_FLASH_BIT (1<<16)
  104. #define CONFIG_16BIT (1<<7)
  105. #define CONFIG_BOOT_MODE_BIT (1<<6)
  106. #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
  107. #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
  108. #define CONFIG_PAGE_CNT_MASK 0xF
  109. #define CONFIG_PAGE_CNT_SHIFT 0
  110. /* NFC_IRQ_STATUS Field */
  111. #define IDLE_IRQ_BIT (1<<29)
  112. #define IDLE_EN_BIT (1<<20)
  113. #define CMD_DONE_CLEAR_BIT (1<<18)
  114. #define IDLE_CLEAR_BIT (1<<17)
  115. #define NFC_TIMEOUT (1000)
  116. /*
  117. * ECC status - seems to consume 8 bytes (double word). The documented
  118. * status byte is located in the lowest byte of the second word (which is
  119. * the 4th or 7th byte depending on endianness).
  120. * Calculate an offset to store the ECC status at the end of the buffer.
  121. */
  122. #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
  123. #define ECC_STATUS 0x4
  124. #define ECC_STATUS_MASK 0x80
  125. #define ECC_STATUS_ERR_COUNT 0x3F
  126. enum vf610_nfc_alt_buf {
  127. ALT_BUF_DATA = 0,
  128. ALT_BUF_ID = 1,
  129. ALT_BUF_STAT = 2,
  130. ALT_BUF_ONFI = 3,
  131. };
  132. struct vf610_nfc {
  133. struct nand_chip chip;
  134. /* NULL without CONFIG_NAND_VF610_NFC_DT */
  135. struct udevice *dev;
  136. void __iomem *regs;
  137. uint buf_offset;
  138. int write_sz;
  139. /* Status and ID are in alternate locations. */
  140. enum vf610_nfc_alt_buf alt_buf;
  141. };
  142. #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
  143. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  144. #define ECC_HW_MODE ECC_45_BYTE
  145. static struct nand_ecclayout vf610_nfc_ecc = {
  146. .eccbytes = 45,
  147. .eccpos = {19, 20, 21, 22, 23,
  148. 24, 25, 26, 27, 28, 29, 30, 31,
  149. 32, 33, 34, 35, 36, 37, 38, 39,
  150. 40, 41, 42, 43, 44, 45, 46, 47,
  151. 48, 49, 50, 51, 52, 53, 54, 55,
  152. 56, 57, 58, 59, 60, 61, 62, 63},
  153. .oobfree = {
  154. {.offset = 2,
  155. .length = 17} }
  156. };
  157. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  158. #define ECC_HW_MODE ECC_60_BYTE
  159. static struct nand_ecclayout vf610_nfc_ecc = {
  160. .eccbytes = 60,
  161. .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
  162. 12, 13, 14, 15, 16, 17, 18, 19,
  163. 20, 21, 22, 23, 24, 25, 26, 27,
  164. 28, 29, 30, 31, 32, 33, 34, 35,
  165. 36, 37, 38, 39, 40, 41, 42, 43,
  166. 44, 45, 46, 47, 48, 49, 50, 51,
  167. 52, 53, 54, 55, 56, 57, 58, 59,
  168. 60, 61, 62, 63 },
  169. .oobfree = {
  170. {.offset = 2,
  171. .length = 2} }
  172. };
  173. #endif
  174. static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
  175. {
  176. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  177. return readl(nfc->regs + reg);
  178. }
  179. static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
  180. {
  181. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  182. writel(val, nfc->regs + reg);
  183. }
  184. static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
  185. {
  186. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
  187. }
  188. static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
  189. {
  190. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
  191. }
  192. static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
  193. u32 mask, u32 shift, u32 val)
  194. {
  195. vf610_nfc_write(mtd, reg,
  196. (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
  197. }
  198. static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
  199. {
  200. /*
  201. * Use this accessor for the internal SRAM buffers. On the ARM
  202. * Freescale Vybrid SoC it's known that the driver can treat
  203. * the SRAM buffer as if it's memory. Other platform might need
  204. * to treat the buffers differently.
  205. *
  206. * For the time being, use memcpy
  207. */
  208. memcpy(dst, src, n);
  209. }
  210. /* Clear flags for upcoming command */
  211. static inline void vf610_nfc_clear_status(void __iomem *regbase)
  212. {
  213. void __iomem *reg = regbase + NFC_IRQ_STATUS;
  214. u32 tmp = __raw_readl(reg);
  215. tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
  216. __raw_writel(tmp, reg);
  217. }
  218. /* Wait for complete operation */
  219. static void vf610_nfc_done(struct mtd_info *mtd)
  220. {
  221. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  222. uint start;
  223. /*
  224. * Barrier is needed after this write. This write need
  225. * to be done before reading the next register the first
  226. * time.
  227. * vf610_nfc_set implicates such a barrier by using writel
  228. * to write to the register.
  229. */
  230. vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
  231. start = get_timer(0);
  232. while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
  233. if (get_timer(start) > NFC_TIMEOUT) {
  234. printf("Timeout while waiting for IDLE.\n");
  235. return;
  236. }
  237. }
  238. vf610_nfc_clear_status(nfc->regs);
  239. }
  240. static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
  241. {
  242. u32 flash_id;
  243. if (col < 4) {
  244. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
  245. flash_id >>= (3 - col) * 8;
  246. } else {
  247. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
  248. flash_id >>= 24;
  249. }
  250. return flash_id & 0xff;
  251. }
  252. static u8 vf610_nfc_get_status(struct mtd_info *mtd)
  253. {
  254. return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
  255. }
  256. /* Single command */
  257. static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
  258. u32 cmd_code)
  259. {
  260. void __iomem *reg = regbase + NFC_FLASH_CMD2;
  261. u32 tmp;
  262. vf610_nfc_clear_status(regbase);
  263. tmp = __raw_readl(reg);
  264. tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
  265. tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
  266. tmp |= cmd_code << CMD_CODE_SHIFT;
  267. __raw_writel(tmp, reg);
  268. }
  269. /* Two commands */
  270. static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
  271. u32 cmd_byte2, u32 cmd_code)
  272. {
  273. void __iomem *reg = regbase + NFC_FLASH_CMD1;
  274. u32 tmp;
  275. vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
  276. tmp = __raw_readl(reg);
  277. tmp &= ~CMD_BYTE2_MASK;
  278. tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
  279. __raw_writel(tmp, reg);
  280. }
  281. static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
  282. {
  283. if (column != -1) {
  284. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  285. if (nfc->chip.options & NAND_BUSWIDTH_16)
  286. column = column / 2;
  287. vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
  288. COL_ADDR_SHIFT, column);
  289. }
  290. if (page != -1)
  291. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  292. ROW_ADDR_SHIFT, page);
  293. }
  294. static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
  295. {
  296. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  297. CONFIG_ECC_MODE_MASK,
  298. CONFIG_ECC_MODE_SHIFT, ecc_mode);
  299. }
  300. static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
  301. {
  302. __raw_writel(size, regbase + NFC_SECTOR_SIZE);
  303. }
  304. /* Send command to NAND chip */
  305. static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
  306. int column, int page)
  307. {
  308. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  309. int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
  310. nfc->buf_offset = max(column, 0);
  311. nfc->alt_buf = ALT_BUF_DATA;
  312. switch (command) {
  313. case NAND_CMD_SEQIN:
  314. /* Use valid column/page from preread... */
  315. vf610_nfc_addr_cycle(mtd, column, page);
  316. nfc->buf_offset = 0;
  317. /*
  318. * SEQIN => data => PAGEPROG sequence is done by the controller
  319. * hence we do not need to issue the command here...
  320. */
  321. return;
  322. case NAND_CMD_PAGEPROG:
  323. trfr_sz += nfc->write_sz;
  324. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  325. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  326. vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
  327. command, PROGRAM_PAGE_CMD_CODE);
  328. break;
  329. case NAND_CMD_RESET:
  330. vf610_nfc_transfer_size(nfc->regs, 0);
  331. vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
  332. break;
  333. case NAND_CMD_READOOB:
  334. trfr_sz += mtd->oobsize;
  335. column = mtd->writesize;
  336. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  337. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  338. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  339. vf610_nfc_addr_cycle(mtd, column, page);
  340. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  341. break;
  342. case NAND_CMD_READ0:
  343. trfr_sz += mtd->writesize + mtd->oobsize;
  344. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  345. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  346. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  347. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  348. vf610_nfc_addr_cycle(mtd, column, page);
  349. break;
  350. case NAND_CMD_PARAM:
  351. nfc->alt_buf = ALT_BUF_ONFI;
  352. trfr_sz = 3 * sizeof(struct nand_onfi_params);
  353. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  354. vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
  355. READ_ONFI_PARAM_CMD_CODE);
  356. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  357. ROW_ADDR_SHIFT, column);
  358. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  359. break;
  360. case NAND_CMD_ERASE1:
  361. vf610_nfc_transfer_size(nfc->regs, 0);
  362. vf610_nfc_send_commands(nfc->regs, command,
  363. NAND_CMD_ERASE2, ERASE_CMD_CODE);
  364. vf610_nfc_addr_cycle(mtd, column, page);
  365. break;
  366. case NAND_CMD_READID:
  367. nfc->alt_buf = ALT_BUF_ID;
  368. nfc->buf_offset = 0;
  369. vf610_nfc_transfer_size(nfc->regs, 0);
  370. vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
  371. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  372. ROW_ADDR_SHIFT, column);
  373. break;
  374. case NAND_CMD_STATUS:
  375. nfc->alt_buf = ALT_BUF_STAT;
  376. vf610_nfc_transfer_size(nfc->regs, 0);
  377. vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
  378. break;
  379. default:
  380. return;
  381. }
  382. vf610_nfc_done(mtd);
  383. nfc->write_sz = 0;
  384. }
  385. /* Read data from NFC buffers */
  386. static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  387. {
  388. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  389. uint c = nfc->buf_offset;
  390. /* Alternate buffers are only supported through read_byte */
  391. if (nfc->alt_buf)
  392. return;
  393. vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
  394. nfc->buf_offset += len;
  395. }
  396. /* Write data to NFC buffers */
  397. static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  398. int len)
  399. {
  400. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  401. uint c = nfc->buf_offset;
  402. uint l;
  403. l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
  404. vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
  405. nfc->write_sz += l;
  406. nfc->buf_offset += l;
  407. }
  408. /* Read byte from NFC buffers */
  409. static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
  410. {
  411. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  412. u8 tmp;
  413. uint c = nfc->buf_offset;
  414. switch (nfc->alt_buf) {
  415. case ALT_BUF_ID:
  416. tmp = vf610_nfc_get_id(mtd, c);
  417. break;
  418. case ALT_BUF_STAT:
  419. tmp = vf610_nfc_get_status(mtd);
  420. break;
  421. #ifdef __LITTLE_ENDIAN
  422. case ALT_BUF_ONFI:
  423. /* Reverse byte since the controller uses big endianness */
  424. c = nfc->buf_offset ^ 0x3;
  425. /* fall-through */
  426. #endif
  427. default:
  428. tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
  429. break;
  430. }
  431. nfc->buf_offset++;
  432. return tmp;
  433. }
  434. /* Read word from NFC buffers */
  435. static u16 vf610_nfc_read_word(struct mtd_info *mtd)
  436. {
  437. u16 tmp;
  438. vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
  439. return tmp;
  440. }
  441. /* If not provided, upper layers apply a fixed delay. */
  442. static int vf610_nfc_dev_ready(struct mtd_info *mtd)
  443. {
  444. /* NFC handles R/B internally; always ready. */
  445. return 1;
  446. }
  447. /*
  448. * This function supports Vybrid only (MPC5125 would have full RB and four CS)
  449. */
  450. static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
  451. {
  452. #ifdef CONFIG_VF610
  453. u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
  454. tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
  455. if (chip >= 0) {
  456. tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
  457. tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
  458. }
  459. vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
  460. #endif
  461. }
  462. /* Count the number of 0's in buff upto max_bits */
  463. static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
  464. {
  465. uint32_t *buff32 = (uint32_t *)buff;
  466. int k, written_bits = 0;
  467. for (k = 0; k < (size / 4); k++) {
  468. written_bits += hweight32(~buff32[k]);
  469. if (written_bits > max_bits)
  470. break;
  471. }
  472. return written_bits;
  473. }
  474. static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
  475. uint8_t *oob, int page)
  476. {
  477. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  478. u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
  479. u8 ecc_status;
  480. u8 ecc_count;
  481. int flips;
  482. int flips_threshold = nfc->chip.ecc.strength / 2;
  483. ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
  484. ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
  485. if (!(ecc_status & ECC_STATUS_MASK))
  486. return ecc_count;
  487. /* Read OOB without ECC unit enabled */
  488. vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
  489. vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
  490. /*
  491. * On an erased page, bit count (including OOB) should be zero or
  492. * at least less then half of the ECC strength.
  493. */
  494. flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
  495. flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
  496. if (unlikely(flips > flips_threshold))
  497. return -EINVAL;
  498. /* Erased page. */
  499. memset(dat, 0xff, nfc->chip.ecc.size);
  500. memset(oob, 0xff, mtd->oobsize);
  501. return flips;
  502. }
  503. static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  504. uint8_t *buf, int oob_required, int page)
  505. {
  506. int eccsize = chip->ecc.size;
  507. int stat;
  508. vf610_nfc_read_buf(mtd, buf, eccsize);
  509. if (oob_required)
  510. vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  511. stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
  512. if (stat < 0) {
  513. mtd->ecc_stats.failed++;
  514. return 0;
  515. } else {
  516. mtd->ecc_stats.corrected += stat;
  517. return stat;
  518. }
  519. }
  520. /*
  521. * ECC will be calculated automatically
  522. */
  523. static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  524. const uint8_t *buf, int oob_required, int page)
  525. {
  526. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  527. vf610_nfc_write_buf(mtd, buf, mtd->writesize);
  528. if (oob_required)
  529. vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  530. /* Always write whole page including OOB due to HW ECC */
  531. nfc->write_sz = mtd->writesize + mtd->oobsize;
  532. return 0;
  533. }
  534. struct vf610_nfc_config {
  535. int hardware_ecc;
  536. int width;
  537. int flash_bbt;
  538. };
  539. static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
  540. {
  541. struct nand_chip *chip = &nfc->chip;
  542. struct mtd_info *mtd = nand_to_mtd(chip);
  543. int err = 0;
  544. struct vf610_nfc_config cfg = {
  545. .hardware_ecc = 1,
  546. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  547. .width = 16,
  548. #else
  549. .width = 8,
  550. #endif
  551. .flash_bbt = 1,
  552. };
  553. nand_set_controller_data(chip, nfc);
  554. if (cfg.width == 16)
  555. chip->options |= NAND_BUSWIDTH_16;
  556. chip->dev_ready = vf610_nfc_dev_ready;
  557. chip->cmdfunc = vf610_nfc_command;
  558. chip->read_byte = vf610_nfc_read_byte;
  559. chip->read_word = vf610_nfc_read_word;
  560. chip->read_buf = vf610_nfc_read_buf;
  561. chip->write_buf = vf610_nfc_write_buf;
  562. chip->select_chip = vf610_nfc_select_chip;
  563. chip->options |= NAND_NO_SUBPAGE_WRITE;
  564. chip->ecc.size = PAGE_2K;
  565. /* Set configuration register. */
  566. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  567. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
  568. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
  569. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
  570. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
  571. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
  572. /* Disable virtual pages, only one elementary transfer unit */
  573. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
  574. CONFIG_PAGE_CNT_SHIFT, 1);
  575. /* first scan to find the device and get the page size */
  576. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
  577. err = -ENXIO;
  578. goto error;
  579. }
  580. if (cfg.width == 16)
  581. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  582. /* Bad block options. */
  583. if (cfg.flash_bbt)
  584. chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
  585. NAND_BBT_CREATE;
  586. /* Single buffer only, max 256 OOB minus ECC status */
  587. if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
  588. dev_err(nfc->dev, "Unsupported flash page size\n");
  589. err = -ENXIO;
  590. goto error;
  591. }
  592. if (cfg.hardware_ecc) {
  593. if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
  594. dev_err(nfc->dev, "Unsupported flash with hwecc\n");
  595. err = -ENXIO;
  596. goto error;
  597. }
  598. if (chip->ecc.size != mtd->writesize) {
  599. dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
  600. dev_err(nfc->dev, "Step size needs to be page size\n");
  601. err = -ENXIO;
  602. goto error;
  603. }
  604. /* Current HW ECC layouts only use 64 bytes of OOB */
  605. if (mtd->oobsize > 64)
  606. mtd->oobsize = 64;
  607. /* propagate ecc.layout to mtd_info */
  608. mtd->ecclayout = chip->ecc.layout;
  609. chip->ecc.read_page = vf610_nfc_read_page;
  610. chip->ecc.write_page = vf610_nfc_write_page;
  611. chip->ecc.mode = NAND_ECC_HW;
  612. chip->ecc.size = PAGE_2K;
  613. chip->ecc.layout = &vf610_nfc_ecc;
  614. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  615. chip->ecc.strength = 24;
  616. chip->ecc.bytes = 45;
  617. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  618. chip->ecc.strength = 32;
  619. chip->ecc.bytes = 60;
  620. #endif
  621. /* Set ECC_STATUS offset */
  622. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  623. CONFIG_ECC_SRAM_ADDR_MASK,
  624. CONFIG_ECC_SRAM_ADDR_SHIFT,
  625. ECC_SRAM_ADDR >> 3);
  626. /* Enable ECC status in SRAM */
  627. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
  628. }
  629. /* second phase scan */
  630. err = nand_scan_tail(mtd);
  631. if (err)
  632. return err;
  633. err = nand_register(devnum, mtd);
  634. if (err)
  635. return err;
  636. return 0;
  637. error:
  638. return err;
  639. }
  640. #if CONFIG_NAND_VF610_NFC_DT
  641. static const struct udevice_id vf610_nfc_dt_ids[] = {
  642. {
  643. .compatible = "fsl,vf610-nfc",
  644. },
  645. { /* sentinel */ }
  646. };
  647. static int vf610_nfc_dt_probe(struct udevice *dev)
  648. {
  649. struct resource res;
  650. struct vf610_nfc *nfc = dev_get_priv(dev);
  651. int ret;
  652. ret = dev_read_resource(dev, 0, &res);
  653. if (ret)
  654. return ret;
  655. nfc->regs = devm_ioremap(dev, res.start, resource_size(&res));
  656. nfc->dev = dev;
  657. return vf610_nfc_nand_init(nfc, 0);
  658. }
  659. U_BOOT_DRIVER(vf610_nfc_dt) = {
  660. .name = "vf610-nfc-dt",
  661. .id = UCLASS_MTD,
  662. .of_match = vf610_nfc_dt_ids,
  663. .priv_auto = sizeof(struct vf610_nfc),
  664. .probe = vf610_nfc_dt_probe,
  665. };
  666. void board_nand_init(void)
  667. {
  668. struct udevice *dev;
  669. int ret;
  670. ret = uclass_get_device_by_driver(UCLASS_MTD,
  671. DM_DRIVER_GET(vf610_nfc_dt),
  672. &dev);
  673. if (ret && ret != -ENODEV)
  674. pr_err("Failed to initialize NAND controller. (error %d)\n",
  675. ret);
  676. }
  677. #else
  678. void board_nand_init(void)
  679. {
  680. int err;
  681. struct vf610_nfc *nfc;
  682. nfc = calloc(1, sizeof(*nfc));
  683. if (!nfc) {
  684. printf("%s: Out of memory\n", __func__);
  685. return;
  686. }
  687. nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
  688. err = vf610_nfc_nand_init(nfc, 0);
  689. if (err)
  690. printf("VF610 NAND init failed (err %d)\n", err);
  691. }
  692. #endif /* CONFIG_NAND_VF610_NFC_DT */