tegra_nand.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
  5. * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  6. * (C) Copyright 2006 DENX Software Engineering
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <memalign.h>
  12. #include <nand.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/funcmux.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bug.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/gpio.h>
  21. #include <fdtdec.h>
  22. #include <bouncebuf.h>
  23. #include <dm.h>
  24. #include "tegra_nand.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define NAND_CMD_TIMEOUT_MS 10
  27. #define SKIPPED_SPARE_BYTES 4
  28. /* ECC bytes to be generated for tag data */
  29. #define TAG_ECC_BYTES 4
  30. static const struct udevice_id tegra_nand_dt_ids[] = {
  31. {
  32. .compatible = "nvidia,tegra20-nand",
  33. },
  34. { /* sentinel */ }
  35. };
  36. /* 64 byte oob block info for large page (== 2KB) device
  37. *
  38. * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  39. * Skipped bytes(4)
  40. * Main area Ecc(36)
  41. * Tag data(20)
  42. * Tag data Ecc(4)
  43. *
  44. * Yaffs2 will use 16 tag bytes.
  45. */
  46. static struct nand_ecclayout eccoob = {
  47. .eccbytes = 36,
  48. .eccpos = {
  49. 4, 5, 6, 7, 8, 9, 10, 11, 12,
  50. 13, 14, 15, 16, 17, 18, 19, 20, 21,
  51. 22, 23, 24, 25, 26, 27, 28, 29, 30,
  52. 31, 32, 33, 34, 35, 36, 37, 38, 39,
  53. },
  54. .oobavail = 20,
  55. .oobfree = {
  56. {
  57. .offset = 40,
  58. .length = 20,
  59. },
  60. }
  61. };
  62. enum {
  63. ECC_OK,
  64. ECC_TAG_ERROR = 1 << 0,
  65. ECC_DATA_ERROR = 1 << 1
  66. };
  67. /* Timing parameters */
  68. enum {
  69. FDT_NAND_MAX_TRP_TREA,
  70. FDT_NAND_TWB,
  71. FDT_NAND_MAX_TCR_TAR_TRR,
  72. FDT_NAND_TWHR,
  73. FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  74. FDT_NAND_TWH,
  75. FDT_NAND_TWP,
  76. FDT_NAND_TRH,
  77. FDT_NAND_TADL,
  78. FDT_NAND_TIMING_COUNT
  79. };
  80. /* Information about an attached NAND chip */
  81. struct fdt_nand {
  82. struct nand_ctlr *reg;
  83. int enabled; /* 1 to enable, 0 to disable */
  84. struct gpio_desc wp_gpio; /* write-protect GPIO */
  85. s32 width; /* bit width, normally 8 */
  86. u32 timing[FDT_NAND_TIMING_COUNT];
  87. };
  88. struct nand_drv {
  89. struct nand_ctlr *reg;
  90. struct fdt_nand config;
  91. };
  92. struct tegra_nand_info {
  93. struct udevice *dev;
  94. struct nand_drv nand_ctrl;
  95. struct nand_chip nand_chip;
  96. };
  97. /**
  98. * Wait for command completion
  99. *
  100. * @param reg nand_ctlr structure
  101. * @return
  102. * 1 - Command completed
  103. * 0 - Timeout
  104. */
  105. static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  106. {
  107. u32 reg_val;
  108. int running;
  109. int i;
  110. for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
  111. if ((readl(&reg->command) & CMD_GO) ||
  112. !(readl(&reg->status) & STATUS_RBSY0) ||
  113. !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
  114. udelay(1);
  115. continue;
  116. }
  117. reg_val = readl(&reg->dma_mst_ctrl);
  118. /*
  119. * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
  120. * is set, that means DMA engine is running.
  121. *
  122. * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
  123. * is cleared, indicating DMA transfer completion.
  124. */
  125. running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
  126. DMA_MST_CTRL_EN_B_ENABLE);
  127. if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
  128. return 1;
  129. udelay(1);
  130. }
  131. return 0;
  132. }
  133. /**
  134. * Read one byte from the chip
  135. *
  136. * @param mtd MTD device structure
  137. * @return data byte
  138. *
  139. * Read function for 8bit bus-width
  140. */
  141. static uint8_t read_byte(struct mtd_info *mtd)
  142. {
  143. struct nand_chip *chip = mtd_to_nand(mtd);
  144. struct nand_drv *info;
  145. info = (struct nand_drv *)nand_get_controller_data(chip);
  146. writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
  147. &info->reg->command);
  148. if (!nand_waitfor_cmd_completion(info->reg))
  149. printf("Command timeout\n");
  150. return (uint8_t)readl(&info->reg->resp);
  151. }
  152. /**
  153. * Read len bytes from the chip into a buffer
  154. *
  155. * @param mtd MTD device structure
  156. * @param buf buffer to store data to
  157. * @param len number of bytes to read
  158. *
  159. * Read function for 8bit bus-width
  160. */
  161. static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  162. {
  163. int i, s;
  164. unsigned int reg;
  165. struct nand_chip *chip = mtd_to_nand(mtd);
  166. struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
  167. for (i = 0; i < len; i += 4) {
  168. s = (len - i) > 4 ? 4 : len - i;
  169. writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
  170. ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
  171. &info->reg->command);
  172. if (!nand_waitfor_cmd_completion(info->reg))
  173. puts("Command timeout during read_buf\n");
  174. reg = readl(&info->reg->resp);
  175. memcpy(buf + i, &reg, s);
  176. }
  177. }
  178. /**
  179. * Check NAND status to see if it is ready or not
  180. *
  181. * @param mtd MTD device structure
  182. * @return
  183. * 1 - ready
  184. * 0 - not ready
  185. */
  186. static int nand_dev_ready(struct mtd_info *mtd)
  187. {
  188. struct nand_chip *chip = mtd_to_nand(mtd);
  189. int reg_val;
  190. struct nand_drv *info;
  191. info = (struct nand_drv *)nand_get_controller_data(chip);
  192. reg_val = readl(&info->reg->status);
  193. if (reg_val & STATUS_RBSY0)
  194. return 1;
  195. else
  196. return 0;
  197. }
  198. /* Dummy implementation: we don't support multiple chips */
  199. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  200. {
  201. switch (chipnr) {
  202. case -1:
  203. case 0:
  204. break;
  205. default:
  206. BUG();
  207. }
  208. }
  209. /**
  210. * Clear all interrupt status bits
  211. *
  212. * @param reg nand_ctlr structure
  213. */
  214. static void nand_clear_interrupt_status(struct nand_ctlr *reg)
  215. {
  216. u32 reg_val;
  217. /* Clear interrupt status */
  218. reg_val = readl(&reg->isr);
  219. writel(reg_val, &reg->isr);
  220. }
  221. /**
  222. * Send command to NAND device
  223. *
  224. * @param mtd MTD device structure
  225. * @param command the command to be sent
  226. * @param column the column address for this command, -1 if none
  227. * @param page_addr the page address for this command, -1 if none
  228. */
  229. static void nand_command(struct mtd_info *mtd, unsigned int command,
  230. int column, int page_addr)
  231. {
  232. struct nand_chip *chip = mtd_to_nand(mtd);
  233. struct nand_drv *info;
  234. info = (struct nand_drv *)nand_get_controller_data(chip);
  235. /*
  236. * Write out the command to the device.
  237. *
  238. * Only command NAND_CMD_RESET or NAND_CMD_READID will come
  239. * here before mtd->writesize is initialized.
  240. */
  241. /* Emulate NAND_CMD_READOOB */
  242. if (command == NAND_CMD_READOOB) {
  243. assert(mtd->writesize != 0);
  244. column += mtd->writesize;
  245. command = NAND_CMD_READ0;
  246. }
  247. /* Adjust columns for 16 bit bus-width */
  248. if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
  249. column >>= 1;
  250. nand_clear_interrupt_status(info->reg);
  251. /* Stop DMA engine, clear DMA completion status */
  252. writel(DMA_MST_CTRL_EN_A_DISABLE
  253. | DMA_MST_CTRL_EN_B_DISABLE
  254. | DMA_MST_CTRL_IS_DMA_DONE,
  255. &info->reg->dma_mst_ctrl);
  256. /*
  257. * Program and erase have their own busy handlers
  258. * status and sequential in needs no delay
  259. */
  260. switch (command) {
  261. case NAND_CMD_READID:
  262. writel(NAND_CMD_READID, &info->reg->cmd_reg1);
  263. writel(column & 0xFF, &info->reg->addr_reg1);
  264. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  265. &info->reg->command);
  266. break;
  267. case NAND_CMD_PARAM:
  268. writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
  269. writel(column & 0xFF, &info->reg->addr_reg1);
  270. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  271. &info->reg->command);
  272. break;
  273. case NAND_CMD_READ0:
  274. writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
  275. writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
  276. writel((page_addr << 16) | (column & 0xFFFF),
  277. &info->reg->addr_reg1);
  278. writel(page_addr >> 16, &info->reg->addr_reg2);
  279. return;
  280. case NAND_CMD_SEQIN:
  281. writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
  282. writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
  283. writel((page_addr << 16) | (column & 0xFFFF),
  284. &info->reg->addr_reg1);
  285. writel(page_addr >> 16,
  286. &info->reg->addr_reg2);
  287. return;
  288. case NAND_CMD_PAGEPROG:
  289. return;
  290. case NAND_CMD_ERASE1:
  291. writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
  292. writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
  293. writel(page_addr, &info->reg->addr_reg1);
  294. writel(CMD_GO | CMD_CLE | CMD_ALE |
  295. CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
  296. &info->reg->command);
  297. break;
  298. case NAND_CMD_ERASE2:
  299. return;
  300. case NAND_CMD_STATUS:
  301. writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
  302. writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
  303. | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
  304. | CMD_CE0,
  305. &info->reg->command);
  306. break;
  307. case NAND_CMD_RESET:
  308. writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
  309. writel(CMD_GO | CMD_CLE | CMD_CE0,
  310. &info->reg->command);
  311. break;
  312. case NAND_CMD_RNDOUT:
  313. default:
  314. printf("%s: Unsupported command %d\n", __func__, command);
  315. return;
  316. }
  317. if (!nand_waitfor_cmd_completion(info->reg))
  318. printf("Command 0x%02X timeout\n", command);
  319. }
  320. /**
  321. * Check whether the pointed buffer are all 0xff (blank).
  322. *
  323. * @param buf data buffer for blank check
  324. * @param len length of the buffer in byte
  325. * @return
  326. * 1 - blank
  327. * 0 - non-blank
  328. */
  329. static int blank_check(u8 *buf, int len)
  330. {
  331. int i;
  332. for (i = 0; i < len; i++)
  333. if (buf[i] != 0xFF)
  334. return 0;
  335. return 1;
  336. }
  337. /**
  338. * After a DMA transfer for read, we call this function to see whether there
  339. * is any uncorrectable error on the pointed data buffer or oob buffer.
  340. *
  341. * @param reg nand_ctlr structure
  342. * @param databuf data buffer
  343. * @param a_len data buffer length
  344. * @param oobbuf oob buffer
  345. * @param b_len oob buffer length
  346. * @return
  347. * ECC_OK - no ECC error or correctable ECC error
  348. * ECC_TAG_ERROR - uncorrectable tag ECC error
  349. * ECC_DATA_ERROR - uncorrectable data ECC error
  350. * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
  351. */
  352. static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
  353. int a_len, u8 *oobbuf, int b_len)
  354. {
  355. int return_val = ECC_OK;
  356. u32 reg_val;
  357. if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
  358. return ECC_OK;
  359. /*
  360. * Area A is used for the data block (databuf). Area B is used for
  361. * the spare block (oobbuf)
  362. */
  363. reg_val = readl(&reg->dec_status);
  364. if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
  365. reg_val = readl(&reg->bch_dec_status_buf);
  366. /*
  367. * If uncorrectable error occurs on data area, then see whether
  368. * they are all FF. If all are FF, it's a blank page.
  369. * Not error.
  370. */
  371. if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
  372. !blank_check(databuf, a_len))
  373. return_val |= ECC_DATA_ERROR;
  374. }
  375. if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
  376. reg_val = readl(&reg->bch_dec_status_buf);
  377. /*
  378. * If uncorrectable error occurs on tag area, then see whether
  379. * they are all FF. If all are FF, it's a blank page.
  380. * Not error.
  381. */
  382. if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
  383. !blank_check(oobbuf, b_len))
  384. return_val |= ECC_TAG_ERROR;
  385. }
  386. return return_val;
  387. }
  388. /**
  389. * Set GO bit to send command to device
  390. *
  391. * @param reg nand_ctlr structure
  392. */
  393. static void start_command(struct nand_ctlr *reg)
  394. {
  395. u32 reg_val;
  396. reg_val = readl(&reg->command);
  397. reg_val |= CMD_GO;
  398. writel(reg_val, &reg->command);
  399. }
  400. /**
  401. * Clear command GO bit, DMA GO bit, and DMA completion status
  402. *
  403. * @param reg nand_ctlr structure
  404. */
  405. static void stop_command(struct nand_ctlr *reg)
  406. {
  407. /* Stop command */
  408. writel(0, &reg->command);
  409. /* Stop DMA engine and clear DMA completion status */
  410. writel(DMA_MST_CTRL_GO_DISABLE
  411. | DMA_MST_CTRL_IS_DMA_DONE,
  412. &reg->dma_mst_ctrl);
  413. }
  414. /**
  415. * Set up NAND bus width and page size
  416. *
  417. * @param info nand_info structure
  418. * @param *reg_val address of reg_val
  419. * @return 0 if ok, -1 on error
  420. */
  421. static int set_bus_width_page_size(struct mtd_info *our_mtd,
  422. struct fdt_nand *config, u32 *reg_val)
  423. {
  424. if (config->width == 8)
  425. *reg_val = CFG_BUS_WIDTH_8BIT;
  426. else if (config->width == 16)
  427. *reg_val = CFG_BUS_WIDTH_16BIT;
  428. else {
  429. debug("%s: Unsupported bus width %d\n", __func__,
  430. config->width);
  431. return -1;
  432. }
  433. if (our_mtd->writesize == 512)
  434. *reg_val |= CFG_PAGE_SIZE_512;
  435. else if (our_mtd->writesize == 2048)
  436. *reg_val |= CFG_PAGE_SIZE_2048;
  437. else if (our_mtd->writesize == 4096)
  438. *reg_val |= CFG_PAGE_SIZE_4096;
  439. else {
  440. debug("%s: Unsupported page size %d\n", __func__,
  441. our_mtd->writesize);
  442. return -1;
  443. }
  444. return 0;
  445. }
  446. /**
  447. * Page read/write function
  448. *
  449. * @param mtd mtd info structure
  450. * @param chip nand chip info structure
  451. * @param buf data buffer
  452. * @param page page number
  453. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  454. * @param is_writing 0 for read, 1 for write
  455. * @return 0 when successfully completed
  456. * -EIO when command timeout
  457. */
  458. static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
  459. uint8_t *buf, int page, int with_ecc, int is_writing)
  460. {
  461. u32 reg_val;
  462. int tag_size;
  463. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  464. /* 4*128=512 (byte) is the value that our HW can support. */
  465. ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
  466. char *tag_ptr;
  467. struct nand_drv *info;
  468. struct fdt_nand *config;
  469. unsigned int bbflags;
  470. struct bounce_buffer bbstate, bbstate_oob;
  471. if ((uintptr_t)buf & 0x03) {
  472. printf("buf %p has to be 4-byte aligned\n", buf);
  473. return -EINVAL;
  474. }
  475. info = (struct nand_drv *)nand_get_controller_data(chip);
  476. config = &info->config;
  477. if (set_bus_width_page_size(mtd, config, &reg_val))
  478. return -EINVAL;
  479. /* Need to be 4-byte aligned */
  480. tag_ptr = (char *)tag_buf;
  481. stop_command(info->reg);
  482. if (is_writing)
  483. bbflags = GEN_BB_READ;
  484. else
  485. bbflags = GEN_BB_WRITE;
  486. bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
  487. bbflags);
  488. writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
  489. writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
  490. /* Set ECC selection, configure ECC settings */
  491. if (with_ecc) {
  492. if (is_writing)
  493. memcpy(tag_ptr, chip->oob_poi + free->offset,
  494. chip->ecc.layout->oobavail + TAG_ECC_BYTES);
  495. tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
  496. reg_val |= (CFG_SKIP_SPARE_SEL_4
  497. | CFG_SKIP_SPARE_ENABLE
  498. | CFG_HW_ECC_CORRECTION_ENABLE
  499. | CFG_ECC_EN_TAG_DISABLE
  500. | CFG_HW_ECC_SEL_RS
  501. | CFG_HW_ECC_ENABLE
  502. | CFG_TVAL4
  503. | (tag_size - 1));
  504. if (!is_writing)
  505. tag_size += SKIPPED_SPARE_BYTES;
  506. bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
  507. bbflags);
  508. } else {
  509. tag_size = mtd->oobsize;
  510. reg_val |= (CFG_SKIP_SPARE_DISABLE
  511. | CFG_HW_ECC_CORRECTION_DISABLE
  512. | CFG_ECC_EN_TAG_DISABLE
  513. | CFG_HW_ECC_DISABLE
  514. | (tag_size - 1));
  515. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
  516. tag_size, bbflags);
  517. }
  518. writel(reg_val, &info->reg->config);
  519. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  520. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  521. writel(tag_size - 1, &info->reg->dma_cfg_b);
  522. nand_clear_interrupt_status(info->reg);
  523. reg_val = CMD_CLE | CMD_ALE
  524. | CMD_SEC_CMD
  525. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  526. | CMD_A_VALID
  527. | CMD_B_VALID
  528. | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
  529. | CMD_CE0;
  530. if (!is_writing)
  531. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  532. else
  533. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  534. writel(reg_val, &info->reg->command);
  535. /* Setup DMA engine */
  536. reg_val = DMA_MST_CTRL_GO_ENABLE
  537. | DMA_MST_CTRL_BURST_8WORDS
  538. | DMA_MST_CTRL_EN_A_ENABLE
  539. | DMA_MST_CTRL_EN_B_ENABLE;
  540. if (!is_writing)
  541. reg_val |= DMA_MST_CTRL_DIR_READ;
  542. else
  543. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  544. writel(reg_val, &info->reg->dma_mst_ctrl);
  545. start_command(info->reg);
  546. if (!nand_waitfor_cmd_completion(info->reg)) {
  547. if (!is_writing)
  548. printf("Read Page 0x%X timeout ", page);
  549. else
  550. printf("Write Page 0x%X timeout ", page);
  551. if (with_ecc)
  552. printf("with ECC");
  553. else
  554. printf("without ECC");
  555. printf("\n");
  556. return -EIO;
  557. }
  558. bounce_buffer_stop(&bbstate_oob);
  559. bounce_buffer_stop(&bbstate);
  560. if (with_ecc && !is_writing) {
  561. memcpy(chip->oob_poi, tag_ptr,
  562. SKIPPED_SPARE_BYTES);
  563. memcpy(chip->oob_poi + free->offset,
  564. tag_ptr + SKIPPED_SPARE_BYTES,
  565. chip->ecc.layout->oobavail);
  566. reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
  567. 1 << chip->page_shift,
  568. (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
  569. chip->ecc.layout->oobavail);
  570. if (reg_val & ECC_TAG_ERROR)
  571. printf("Read Page 0x%X tag ECC error\n", page);
  572. if (reg_val & ECC_DATA_ERROR)
  573. printf("Read Page 0x%X data ECC error\n",
  574. page);
  575. if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
  576. return -EIO;
  577. }
  578. return 0;
  579. }
  580. /**
  581. * Hardware ecc based page read function
  582. *
  583. * @param mtd mtd info structure
  584. * @param chip nand chip info structure
  585. * @param buf buffer to store read data
  586. * @param page page number to read
  587. * @return 0 when successfully completed
  588. * -EIO when command timeout
  589. */
  590. static int nand_read_page_hwecc(struct mtd_info *mtd,
  591. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  592. {
  593. return nand_rw_page(mtd, chip, buf, page, 1, 0);
  594. }
  595. /**
  596. * Hardware ecc based page write function
  597. *
  598. * @param mtd mtd info structure
  599. * @param chip nand chip info structure
  600. * @param buf data buffer
  601. */
  602. static int nand_write_page_hwecc(struct mtd_info *mtd,
  603. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  604. int page)
  605. {
  606. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
  607. return 0;
  608. }
  609. /**
  610. * Read raw page data without ecc
  611. *
  612. * @param mtd mtd info structure
  613. * @param chip nand chip info structure
  614. * @param buf buffer to store read data
  615. * @param page page number to read
  616. * @return 0 when successfully completed
  617. * -EINVAL when chip->oob_poi is not double-word aligned
  618. * -EIO when command timeout
  619. */
  620. static int nand_read_page_raw(struct mtd_info *mtd,
  621. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  622. {
  623. return nand_rw_page(mtd, chip, buf, page, 0, 0);
  624. }
  625. /**
  626. * Raw page write function
  627. *
  628. * @param mtd mtd info structure
  629. * @param chip nand chip info structure
  630. * @param buf data buffer
  631. */
  632. static int nand_write_page_raw(struct mtd_info *mtd,
  633. struct nand_chip *chip, const uint8_t *buf,
  634. int oob_required, int page)
  635. {
  636. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
  637. return 0;
  638. }
  639. /**
  640. * OOB data read/write function
  641. *
  642. * @param mtd mtd info structure
  643. * @param chip nand chip info structure
  644. * @param page page number to read
  645. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  646. * @param is_writing 0 for read, 1 for write
  647. * @return 0 when successfully completed
  648. * -EINVAL when chip->oob_poi is not double-word aligned
  649. * -EIO when command timeout
  650. */
  651. static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
  652. int page, int with_ecc, int is_writing)
  653. {
  654. u32 reg_val;
  655. int tag_size;
  656. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  657. struct nand_drv *info;
  658. unsigned int bbflags;
  659. struct bounce_buffer bbstate_oob;
  660. if (((int)chip->oob_poi) & 0x03)
  661. return -EINVAL;
  662. info = (struct nand_drv *)nand_get_controller_data(chip);
  663. if (set_bus_width_page_size(mtd, &info->config, &reg_val))
  664. return -EINVAL;
  665. stop_command(info->reg);
  666. /* Set ECC selection */
  667. tag_size = mtd->oobsize;
  668. if (with_ecc)
  669. reg_val |= CFG_ECC_EN_TAG_ENABLE;
  670. else
  671. reg_val |= (CFG_ECC_EN_TAG_DISABLE);
  672. reg_val |= ((tag_size - 1) |
  673. CFG_SKIP_SPARE_DISABLE |
  674. CFG_HW_ECC_CORRECTION_DISABLE |
  675. CFG_HW_ECC_DISABLE);
  676. writel(reg_val, &info->reg->config);
  677. if (is_writing && with_ecc)
  678. tag_size -= TAG_ECC_BYTES;
  679. if (is_writing)
  680. bbflags = GEN_BB_READ;
  681. else
  682. bbflags = GEN_BB_WRITE;
  683. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
  684. bbflags);
  685. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  686. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  687. writel(tag_size - 1, &info->reg->dma_cfg_b);
  688. nand_clear_interrupt_status(info->reg);
  689. reg_val = CMD_CLE | CMD_ALE
  690. | CMD_SEC_CMD
  691. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  692. | CMD_B_VALID
  693. | CMD_CE0;
  694. if (!is_writing)
  695. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  696. else
  697. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  698. writel(reg_val, &info->reg->command);
  699. /* Setup DMA engine */
  700. reg_val = DMA_MST_CTRL_GO_ENABLE
  701. | DMA_MST_CTRL_BURST_8WORDS
  702. | DMA_MST_CTRL_EN_B_ENABLE;
  703. if (!is_writing)
  704. reg_val |= DMA_MST_CTRL_DIR_READ;
  705. else
  706. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  707. writel(reg_val, &info->reg->dma_mst_ctrl);
  708. start_command(info->reg);
  709. if (!nand_waitfor_cmd_completion(info->reg)) {
  710. if (!is_writing)
  711. printf("Read OOB of Page 0x%X timeout\n", page);
  712. else
  713. printf("Write OOB of Page 0x%X timeout\n", page);
  714. return -EIO;
  715. }
  716. bounce_buffer_stop(&bbstate_oob);
  717. if (with_ecc && !is_writing) {
  718. reg_val = (u32)check_ecc_error(info->reg, 0, 0,
  719. (u8 *)(chip->oob_poi + free->offset),
  720. chip->ecc.layout->oobavail);
  721. if (reg_val & ECC_TAG_ERROR)
  722. printf("Read OOB of Page 0x%X tag ECC error\n", page);
  723. }
  724. return 0;
  725. }
  726. /**
  727. * OOB data read function
  728. *
  729. * @param mtd mtd info structure
  730. * @param chip nand chip info structure
  731. * @param page page number to read
  732. */
  733. static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  734. int page)
  735. {
  736. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  737. nand_rw_oob(mtd, chip, page, 0, 0);
  738. return 0;
  739. }
  740. /**
  741. * OOB data write function
  742. *
  743. * @param mtd mtd info structure
  744. * @param chip nand chip info structure
  745. * @param page page number to write
  746. * @return 0 when successfully completed
  747. * -EINVAL when chip->oob_poi is not double-word aligned
  748. * -EIO when command timeout
  749. */
  750. static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  751. int page)
  752. {
  753. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  754. return nand_rw_oob(mtd, chip, page, 0, 1);
  755. }
  756. /**
  757. * Set up NAND memory timings according to the provided parameters
  758. *
  759. * @param timing Timing parameters
  760. * @param reg NAND controller register address
  761. */
  762. static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
  763. struct nand_ctlr *reg)
  764. {
  765. u32 reg_val, clk_rate, clk_period, time_val;
  766. clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
  767. CLOCK_ID_PERIPH) / 1000000;
  768. clk_period = 1000 / clk_rate;
  769. reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  770. TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
  771. reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
  772. TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
  773. time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
  774. if (time_val > 2)
  775. reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
  776. TIMING_TCR_TAR_TRR_CNT_MASK;
  777. reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
  778. TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
  779. time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
  780. if (time_val > 1)
  781. reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
  782. TIMING_TCS_CNT_MASK;
  783. reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
  784. TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
  785. reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
  786. TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
  787. reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
  788. TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
  789. reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  790. TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
  791. writel(reg_val, &reg->timing);
  792. reg_val = 0;
  793. time_val = timing[FDT_NAND_TADL] / clk_period;
  794. if (time_val > 2)
  795. reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
  796. writel(reg_val, &reg->timing2);
  797. }
  798. /**
  799. * Decode NAND parameters from the device tree
  800. *
  801. * @param dev Driver model device
  802. * @param config Device tree NAND configuration
  803. * @return 0 if ok, -ve on error (FDT_ERR_...)
  804. */
  805. static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
  806. {
  807. int err;
  808. config->reg = (struct nand_ctlr *)dev_read_addr(dev);
  809. config->enabled = dev_read_enabled(dev);
  810. config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
  811. err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
  812. GPIOD_IS_OUT);
  813. if (err)
  814. return err;
  815. err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
  816. FDT_NAND_TIMING_COUNT);
  817. if (err < 0)
  818. return err;
  819. return 0;
  820. }
  821. static int tegra_probe(struct udevice *dev)
  822. {
  823. struct tegra_nand_info *tegra = dev_get_priv(dev);
  824. struct nand_chip *nand = &tegra->nand_chip;
  825. struct nand_drv *info = &tegra->nand_ctrl;
  826. struct fdt_nand *config = &info->config;
  827. struct mtd_info *our_mtd;
  828. int ret;
  829. if (fdt_decode_nand(dev, config)) {
  830. printf("Could not decode nand-flash in device tree\n");
  831. return -1;
  832. }
  833. if (!config->enabled)
  834. return -1;
  835. info->reg = config->reg;
  836. nand->ecc.mode = NAND_ECC_HW;
  837. nand->ecc.layout = &eccoob;
  838. nand->options = LP_OPTIONS;
  839. nand->cmdfunc = nand_command;
  840. nand->read_byte = read_byte;
  841. nand->read_buf = read_buf;
  842. nand->ecc.read_page = nand_read_page_hwecc;
  843. nand->ecc.write_page = nand_write_page_hwecc;
  844. nand->ecc.read_page_raw = nand_read_page_raw;
  845. nand->ecc.write_page_raw = nand_write_page_raw;
  846. nand->ecc.read_oob = nand_read_oob;
  847. nand->ecc.write_oob = nand_write_oob;
  848. nand->ecc.strength = 1;
  849. nand->select_chip = nand_select_chip;
  850. nand->dev_ready = nand_dev_ready;
  851. nand_set_controller_data(nand, &tegra->nand_ctrl);
  852. /* Disable subpage writes as we do not provide ecc->hwctl */
  853. nand->options |= NAND_NO_SUBPAGE_WRITE;
  854. /* Adjust controller clock rate */
  855. clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
  856. /* Adjust timing for NAND device */
  857. setup_timing(config->timing, info->reg);
  858. dm_gpio_set_value(&config->wp_gpio, 1);
  859. our_mtd = nand_to_mtd(nand);
  860. ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  861. if (ret)
  862. return ret;
  863. nand->ecc.size = our_mtd->writesize;
  864. nand->ecc.bytes = our_mtd->oobsize;
  865. ret = nand_scan_tail(our_mtd);
  866. if (ret)
  867. return ret;
  868. ret = nand_register(0, our_mtd);
  869. if (ret) {
  870. dev_err(dev, "Failed to register MTD: %d\n", ret);
  871. return ret;
  872. }
  873. return 0;
  874. }
  875. U_BOOT_DRIVER(tegra_nand) = {
  876. .name = "tegra-nand",
  877. .id = UCLASS_MTD,
  878. .of_match = tegra_nand_dt_ids,
  879. .probe = tegra_probe,
  880. .priv_auto = sizeof(struct tegra_nand_info),
  881. };
  882. void board_nand_init(void)
  883. {
  884. struct udevice *dev;
  885. int ret;
  886. ret = uclass_get_device_by_driver(UCLASS_MTD,
  887. DM_DRIVER_GET(tegra_nand), &dev);
  888. if (ret && ret != -ENODEV)
  889. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  890. ret);
  891. }