pxa3xx_nand.c 51 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/mtd/nand/raw/pxa3xx_nand.c
  4. *
  5. * Copyright © 2005 Intel Corporation
  6. * Copyright © 2006 Marvell International Ltd.
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <fdtdec.h>
  11. #include <nand.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/bitops.h>
  15. #include <linux/bug.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/cpu.h>
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/rawnand.h>
  23. #include <linux/types.h>
  24. #include <syscon.h>
  25. #include <regmap.h>
  26. #include <dm/uclass.h>
  27. #include <dm/read.h>
  28. #include "pxa3xx_nand.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  31. #define CHIP_DELAY_TIMEOUT 200
  32. #define NAND_STOP_DELAY 40
  33. /*
  34. * Define a buffer size for the initial command that detects the flash device:
  35. * STATUS, READID and PARAM.
  36. * ONFI param page is 256 bytes, and there are three redundant copies
  37. * to be read. JEDEC param page is 512 bytes, and there are also three
  38. * redundant copies to be read.
  39. * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  40. */
  41. #define INIT_BUFFER_SIZE 2048
  42. /* registers and bit definitions */
  43. #define NDCR (0x00) /* Control register */
  44. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  45. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  46. #define NDSR (0x14) /* Status Register */
  47. #define NDPCR (0x18) /* Page Count Register */
  48. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  49. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  50. #define NDECCCTRL (0x28) /* ECC control */
  51. #define NDDB (0x40) /* Data Buffer */
  52. #define NDCB0 (0x48) /* Command Buffer0 */
  53. #define NDCB1 (0x4C) /* Command Buffer1 */
  54. #define NDCB2 (0x50) /* Command Buffer2 */
  55. #define NDCR_SPARE_EN (0x1 << 31)
  56. #define NDCR_ECC_EN (0x1 << 30)
  57. #define NDCR_DMA_EN (0x1 << 29)
  58. #define NDCR_ND_RUN (0x1 << 28)
  59. #define NDCR_DWIDTH_C (0x1 << 27)
  60. #define NDCR_DWIDTH_M (0x1 << 26)
  61. #define NDCR_PAGE_SZ (0x1 << 24)
  62. #define NDCR_NCSX (0x1 << 23)
  63. #define NDCR_ND_MODE (0x3 << 21)
  64. #define NDCR_NAND_MODE (0x0)
  65. #define NDCR_CLR_PG_CNT (0x1 << 20)
  66. #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
  67. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  68. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  69. #define NDCR_RA_START (0x1 << 15)
  70. #define NDCR_PG_PER_BLK (0x1 << 14)
  71. #define NDCR_ND_ARB_EN (0x1 << 12)
  72. #define NDCR_INT_MASK (0xFFF)
  73. #define NDSR_MASK (0xfff)
  74. #define NDSR_ERR_CNT_OFF (16)
  75. #define NDSR_ERR_CNT_MASK (0x1f)
  76. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  77. #define NDSR_RDY (0x1 << 12)
  78. #define NDSR_FLASH_RDY (0x1 << 11)
  79. #define NDSR_CS0_PAGED (0x1 << 10)
  80. #define NDSR_CS1_PAGED (0x1 << 9)
  81. #define NDSR_CS0_CMDD (0x1 << 8)
  82. #define NDSR_CS1_CMDD (0x1 << 7)
  83. #define NDSR_CS0_BBD (0x1 << 6)
  84. #define NDSR_CS1_BBD (0x1 << 5)
  85. #define NDSR_UNCORERR (0x1 << 4)
  86. #define NDSR_CORERR (0x1 << 3)
  87. #define NDSR_WRDREQ (0x1 << 2)
  88. #define NDSR_RDDREQ (0x1 << 1)
  89. #define NDSR_WRCMDREQ (0x1)
  90. #define NDCB0_LEN_OVRD (0x1 << 28)
  91. #define NDCB0_ST_ROW_EN (0x1 << 26)
  92. #define NDCB0_AUTO_RS (0x1 << 25)
  93. #define NDCB0_CSEL (0x1 << 24)
  94. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  95. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  96. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  97. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  98. #define NDCB0_NC (0x1 << 20)
  99. #define NDCB0_DBC (0x1 << 19)
  100. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  101. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  102. #define NDCB0_CMD2_MASK (0xff << 8)
  103. #define NDCB0_CMD1_MASK (0xff)
  104. #define NDCB0_ADDR_CYC_SHIFT (16)
  105. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  106. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  107. #define EXT_CMD_TYPE_READ 4 /* Read */
  108. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  109. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  110. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  111. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  112. /* System control register and bit to enable NAND on some SoCs */
  113. #define GENCONF_SOC_DEVICE_MUX 0x208
  114. #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
  115. /*
  116. * This should be large enough to read 'ONFI' and 'JEDEC'.
  117. * Let's use 7 bytes, which is the maximum ID count supported
  118. * by the controller (see NDCR_RD_ID_CNT_MASK).
  119. */
  120. #define READ_ID_BYTES 7
  121. /* macros for registers read/write */
  122. #define nand_writel(info, off, val) \
  123. writel((val), (info)->mmio_base + (off))
  124. #define nand_readl(info, off) \
  125. readl((info)->mmio_base + (off))
  126. /* error code and state */
  127. enum {
  128. ERR_NONE = 0,
  129. ERR_DMABUSERR = -1,
  130. ERR_SENDCMD = -2,
  131. ERR_UNCORERR = -3,
  132. ERR_BBERR = -4,
  133. ERR_CORERR = -5,
  134. };
  135. enum {
  136. STATE_IDLE = 0,
  137. STATE_PREPARED,
  138. STATE_CMD_HANDLE,
  139. STATE_DMA_READING,
  140. STATE_DMA_WRITING,
  141. STATE_DMA_DONE,
  142. STATE_PIO_READING,
  143. STATE_PIO_WRITING,
  144. STATE_CMD_DONE,
  145. STATE_READY,
  146. };
  147. enum pxa3xx_nand_variant {
  148. PXA3XX_NAND_VARIANT_PXA,
  149. PXA3XX_NAND_VARIANT_ARMADA370,
  150. PXA3XX_NAND_VARIANT_ARMADA_8K,
  151. };
  152. struct pxa3xx_nand_host {
  153. struct nand_chip chip;
  154. void *info_data;
  155. /* page size of attached chip */
  156. int use_ecc;
  157. int cs;
  158. /* calculated from pxa3xx_nand_flash data */
  159. unsigned int col_addr_cycles;
  160. unsigned int row_addr_cycles;
  161. };
  162. struct pxa3xx_nand_info {
  163. struct nand_hw_control controller;
  164. struct pxa3xx_nand_platform_data *pdata;
  165. struct clk *clk;
  166. void __iomem *mmio_base;
  167. unsigned long mmio_phys;
  168. int cmd_complete, dev_ready;
  169. unsigned int buf_start;
  170. unsigned int buf_count;
  171. unsigned int buf_size;
  172. unsigned int data_buff_pos;
  173. unsigned int oob_buff_pos;
  174. unsigned char *data_buff;
  175. unsigned char *oob_buff;
  176. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  177. unsigned int state;
  178. /*
  179. * This driver supports NFCv1 (as found in PXA SoC)
  180. * and NFCv2 (as found in Armada 370/XP SoC).
  181. */
  182. enum pxa3xx_nand_variant variant;
  183. int cs;
  184. int use_ecc; /* use HW ECC ? */
  185. int force_raw; /* prevent use_ecc to be set */
  186. int ecc_bch; /* using BCH ECC? */
  187. int use_spare; /* use spare ? */
  188. int need_wait;
  189. /* Amount of real data per full chunk */
  190. unsigned int chunk_size;
  191. /* Amount of spare data per full chunk */
  192. unsigned int spare_size;
  193. /* Number of full chunks (i.e chunk_size + spare_size) */
  194. unsigned int nfullchunks;
  195. /*
  196. * Total number of chunks. If equal to nfullchunks, then there
  197. * are only full chunks. Otherwise, there is one last chunk of
  198. * size (last_chunk_size + last_spare_size)
  199. */
  200. unsigned int ntotalchunks;
  201. /* Amount of real data in the last chunk */
  202. unsigned int last_chunk_size;
  203. /* Amount of spare data in the last chunk */
  204. unsigned int last_spare_size;
  205. unsigned int ecc_size;
  206. unsigned int ecc_err_cnt;
  207. unsigned int max_bitflips;
  208. int retcode;
  209. /*
  210. * Variables only valid during command
  211. * execution. step_chunk_size and step_spare_size is the
  212. * amount of real data and spare data in the current
  213. * chunk. cur_chunk is the current chunk being
  214. * read/programmed.
  215. */
  216. unsigned int step_chunk_size;
  217. unsigned int step_spare_size;
  218. unsigned int cur_chunk;
  219. /* cached register value */
  220. uint32_t reg_ndcr;
  221. uint32_t ndtr0cs0;
  222. uint32_t ndtr1cs0;
  223. /* generated NDCBx register values */
  224. uint32_t ndcb0;
  225. uint32_t ndcb1;
  226. uint32_t ndcb2;
  227. uint32_t ndcb3;
  228. };
  229. static struct pxa3xx_nand_timing timing[] = {
  230. /*
  231. * tCH Enable signal hold time
  232. * tCS Enable signal setup time
  233. * tWH ND_nWE high duration
  234. * tWP ND_nWE pulse time
  235. * tRH ND_nRE high duration
  236. * tRP ND_nRE pulse width
  237. * tR ND_nWE high to ND_nRE low for read
  238. * tWHR ND_nWE high to ND_nRE low for status read
  239. * tAR ND_ALE low to ND_nRE low delay
  240. */
  241. /*ch cs wh wp rh rp r whr ar */
  242. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  243. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  244. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  245. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  246. { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
  247. };
  248. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  249. /*
  250. * chip_id
  251. * flash_width Width of Flash memory (DWIDTH_M)
  252. * dfc_width Width of flash controller(DWIDTH_C)
  253. * *timing
  254. * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
  255. */
  256. { 0x46ec, 16, 16, &timing[1] },
  257. { 0xdaec, 8, 8, &timing[1] },
  258. { 0xd7ec, 8, 8, &timing[1] },
  259. { 0xa12c, 8, 8, &timing[2] },
  260. { 0xb12c, 16, 16, &timing[2] },
  261. { 0xdc2c, 8, 8, &timing[2] },
  262. { 0xcc2c, 16, 16, &timing[2] },
  263. { 0xba20, 16, 16, &timing[3] },
  264. { 0xda98, 8, 8, &timing[4] },
  265. };
  266. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  267. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  268. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  269. static struct nand_bbt_descr bbt_main_descr = {
  270. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  271. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  272. .offs = 8,
  273. .len = 6,
  274. .veroffs = 14,
  275. .maxblocks = 8, /* Last 8 blocks in each chip */
  276. .pattern = bbt_pattern
  277. };
  278. static struct nand_bbt_descr bbt_mirror_descr = {
  279. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  280. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  281. .offs = 8,
  282. .len = 6,
  283. .veroffs = 14,
  284. .maxblocks = 8, /* Last 8 blocks in each chip */
  285. .pattern = bbt_mirror_pattern
  286. };
  287. #endif
  288. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  289. .eccbytes = 32,
  290. .eccpos = {
  291. 32, 33, 34, 35, 36, 37, 38, 39,
  292. 40, 41, 42, 43, 44, 45, 46, 47,
  293. 48, 49, 50, 51, 52, 53, 54, 55,
  294. 56, 57, 58, 59, 60, 61, 62, 63},
  295. .oobfree = { {2, 30} }
  296. };
  297. static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
  298. .eccbytes = 64,
  299. .eccpos = {
  300. 32, 33, 34, 35, 36, 37, 38, 39,
  301. 40, 41, 42, 43, 44, 45, 46, 47,
  302. 48, 49, 50, 51, 52, 53, 54, 55,
  303. 56, 57, 58, 59, 60, 61, 62, 63,
  304. 64, 65, 66, 67, 68, 69, 70, 71,
  305. 72, 73, 74, 75, 76, 77, 78, 79,
  306. 80, 81, 82, 83, 84, 85, 86, 87,
  307. 88, 89, 90, 91, 92, 93, 94, 95},
  308. .oobfree = { {1, 4}, {6, 26} }
  309. };
  310. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  311. .eccbytes = 64,
  312. .eccpos = {
  313. 32, 33, 34, 35, 36, 37, 38, 39,
  314. 40, 41, 42, 43, 44, 45, 46, 47,
  315. 48, 49, 50, 51, 52, 53, 54, 55,
  316. 56, 57, 58, 59, 60, 61, 62, 63,
  317. 96, 97, 98, 99, 100, 101, 102, 103,
  318. 104, 105, 106, 107, 108, 109, 110, 111,
  319. 112, 113, 114, 115, 116, 117, 118, 119,
  320. 120, 121, 122, 123, 124, 125, 126, 127},
  321. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  322. .oobfree = { {6, 26}, { 64, 32} }
  323. };
  324. static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
  325. .eccbytes = 128,
  326. .eccpos = {
  327. 32, 33, 34, 35, 36, 37, 38, 39,
  328. 40, 41, 42, 43, 44, 45, 46, 47,
  329. 48, 49, 50, 51, 52, 53, 54, 55,
  330. 56, 57, 58, 59, 60, 61, 62, 63,
  331. 96, 97, 98, 99, 100, 101, 102, 103,
  332. 104, 105, 106, 107, 108, 109, 110, 111,
  333. 112, 113, 114, 115, 116, 117, 118, 119,
  334. 120, 121, 122, 123, 124, 125, 126, 127,
  335. 160, 161, 162, 163, 164, 165, 166, 167,
  336. 168, 169, 170, 171, 172, 173, 174, 175,
  337. 176, 177, 178, 179, 180, 181, 182, 183,
  338. 184, 185, 186, 187, 188, 189, 190, 191,
  339. 224, 225, 226, 227, 228, 229, 230, 231,
  340. 232, 233, 234, 235, 236, 237, 238, 239,
  341. 240, 241, 242, 243, 244, 245, 246, 247,
  342. 248, 249, 250, 251, 252, 253, 254, 255},
  343. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  344. .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
  345. };
  346. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  347. .eccbytes = 128,
  348. .eccpos = {
  349. 32, 33, 34, 35, 36, 37, 38, 39,
  350. 40, 41, 42, 43, 44, 45, 46, 47,
  351. 48, 49, 50, 51, 52, 53, 54, 55,
  352. 56, 57, 58, 59, 60, 61, 62, 63},
  353. .oobfree = { }
  354. };
  355. static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
  356. .eccbytes = 256,
  357. .eccpos = {},
  358. /* HW ECC handles all ECC data and all spare area is free for OOB */
  359. .oobfree = {{0, 160} }
  360. };
  361. #define NDTR0_tCH(c) (min((c), 7) << 19)
  362. #define NDTR0_tCS(c) (min((c), 7) << 16)
  363. #define NDTR0_tWH(c) (min((c), 7) << 11)
  364. #define NDTR0_tWP(c) (min((c), 7) << 8)
  365. #define NDTR0_tRH(c) (min((c), 7) << 3)
  366. #define NDTR0_tRP(c) (min((c), 7) << 0)
  367. #define NDTR1_tR(c) (min((c), 65535) << 16)
  368. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  369. #define NDTR1_tAR(c) (min((c), 15) << 0)
  370. /* convert nano-seconds to nand flash controller clock cycles */
  371. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  372. static const struct udevice_id pxa3xx_nand_dt_ids[] = {
  373. {
  374. .compatible = "marvell,mvebu-pxa3xx-nand",
  375. .data = PXA3XX_NAND_VARIANT_ARMADA370,
  376. },
  377. {
  378. .compatible = "marvell,armada-8k-nand-controller",
  379. .data = PXA3XX_NAND_VARIANT_ARMADA_8K,
  380. },
  381. {}
  382. };
  383. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev)
  384. {
  385. return dev_get_driver_data(dev);
  386. }
  387. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  388. const struct pxa3xx_nand_timing *t)
  389. {
  390. struct pxa3xx_nand_info *info = host->info_data;
  391. unsigned long nand_clk = mvebu_get_nand_clock();
  392. uint32_t ndtr0, ndtr1;
  393. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  394. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  395. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  396. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  397. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  398. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  399. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  400. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  401. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  402. info->ndtr0cs0 = ndtr0;
  403. info->ndtr1cs0 = ndtr1;
  404. nand_writel(info, NDTR0CS0, ndtr0);
  405. nand_writel(info, NDTR1CS0, ndtr1);
  406. }
  407. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  408. const struct nand_sdr_timings *t)
  409. {
  410. struct pxa3xx_nand_info *info = host->info_data;
  411. struct nand_chip *chip = &host->chip;
  412. unsigned long nand_clk = mvebu_get_nand_clock();
  413. uint32_t ndtr0, ndtr1;
  414. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  415. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  416. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  417. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
  418. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  419. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
  420. u32 tR = chip->chip_delay * 1000;
  421. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  422. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  423. /* fallback to a default value if tR = 0 */
  424. if (!tR)
  425. tR = 20000;
  426. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  427. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  428. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  429. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  430. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  431. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  432. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  433. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  434. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  435. info->ndtr0cs0 = ndtr0;
  436. info->ndtr1cs0 = ndtr1;
  437. nand_writel(info, NDTR0CS0, ndtr0);
  438. nand_writel(info, NDTR1CS0, ndtr1);
  439. }
  440. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  441. {
  442. const struct nand_sdr_timings *timings;
  443. struct nand_chip *chip = &host->chip;
  444. struct pxa3xx_nand_info *info = host->info_data;
  445. const struct pxa3xx_nand_flash *f = NULL;
  446. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  447. int mode, id, ntypes, i;
  448. mode = onfi_get_async_timing_mode(chip);
  449. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  450. ntypes = ARRAY_SIZE(builtin_flash_types);
  451. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  452. id = chip->read_byte(mtd);
  453. id |= chip->read_byte(mtd) << 0x8;
  454. for (i = 0; i < ntypes; i++) {
  455. f = &builtin_flash_types[i];
  456. if (f->chip_id == id)
  457. break;
  458. }
  459. if (i == ntypes) {
  460. dev_err(mtd->dev, "Error: timings not found\n");
  461. return -EINVAL;
  462. }
  463. pxa3xx_nand_set_timing(host, f->timing);
  464. if (f->flash_width == 16) {
  465. info->reg_ndcr |= NDCR_DWIDTH_M;
  466. chip->options |= NAND_BUSWIDTH_16;
  467. }
  468. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  469. } else {
  470. mode = fls(mode) - 1;
  471. if (mode < 0)
  472. mode = 0;
  473. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  474. if (IS_ERR(timings))
  475. return PTR_ERR(timings);
  476. pxa3xx_nand_set_sdr_timing(host, timings);
  477. }
  478. return 0;
  479. }
  480. /**
  481. * NOTE: it is a must to set ND_RUN first, then write
  482. * command buffer, otherwise, it does not work.
  483. * We enable all the interrupt at the same time, and
  484. * let pxa3xx_nand_irq to handle all logic.
  485. */
  486. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  487. {
  488. uint32_t ndcr;
  489. ndcr = info->reg_ndcr;
  490. if (info->use_ecc) {
  491. ndcr |= NDCR_ECC_EN;
  492. if (info->ecc_bch)
  493. nand_writel(info, NDECCCTRL, 0x1);
  494. } else {
  495. ndcr &= ~NDCR_ECC_EN;
  496. if (info->ecc_bch)
  497. nand_writel(info, NDECCCTRL, 0x0);
  498. }
  499. ndcr &= ~NDCR_DMA_EN;
  500. if (info->use_spare)
  501. ndcr |= NDCR_SPARE_EN;
  502. else
  503. ndcr &= ~NDCR_SPARE_EN;
  504. ndcr |= NDCR_ND_RUN;
  505. /* clear status bits and run */
  506. nand_writel(info, NDSR, NDSR_MASK);
  507. nand_writel(info, NDCR, 0);
  508. nand_writel(info, NDCR, ndcr);
  509. }
  510. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  511. {
  512. uint32_t ndcr;
  513. ndcr = nand_readl(info, NDCR);
  514. nand_writel(info, NDCR, ndcr | int_mask);
  515. }
  516. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  517. {
  518. if (info->ecc_bch && !info->force_raw) {
  519. u32 ts;
  520. /*
  521. * According to the datasheet, when reading from NDDB
  522. * with BCH enabled, after each 32 bytes reads, we
  523. * have to make sure that the NDSR.RDDREQ bit is set.
  524. *
  525. * Drain the FIFO 8 32 bits reads at a time, and skip
  526. * the polling on the last read.
  527. */
  528. while (len > 8) {
  529. readsl(info->mmio_base + NDDB, data, 8);
  530. ts = get_timer(0);
  531. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  532. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  533. dev_err(info->controller.active->mtd.dev,
  534. "Timeout on RDDREQ while draining the FIFO\n");
  535. return;
  536. }
  537. }
  538. data += 32;
  539. len -= 8;
  540. }
  541. }
  542. readsl(info->mmio_base + NDDB, data, len);
  543. }
  544. static void handle_data_pio(struct pxa3xx_nand_info *info)
  545. {
  546. int data_len = info->step_chunk_size;
  547. /*
  548. * In raw mode, include the spare area and the ECC bytes that are not
  549. * consumed by the controller in the data section. Do not reorganize
  550. * here, do it in the ->read_page_raw() handler instead.
  551. */
  552. if (info->force_raw)
  553. data_len += info->step_spare_size + info->ecc_size;
  554. switch (info->state) {
  555. case STATE_PIO_WRITING:
  556. if (info->step_chunk_size)
  557. writesl(info->mmio_base + NDDB,
  558. info->data_buff + info->data_buff_pos,
  559. DIV_ROUND_UP(data_len, 4));
  560. if (info->step_spare_size)
  561. writesl(info->mmio_base + NDDB,
  562. info->oob_buff + info->oob_buff_pos,
  563. DIV_ROUND_UP(info->step_spare_size, 4));
  564. break;
  565. case STATE_PIO_READING:
  566. if (data_len)
  567. drain_fifo(info,
  568. info->data_buff + info->data_buff_pos,
  569. DIV_ROUND_UP(data_len, 4));
  570. if (info->force_raw)
  571. break;
  572. if (info->step_spare_size)
  573. drain_fifo(info,
  574. info->oob_buff + info->oob_buff_pos,
  575. DIV_ROUND_UP(info->step_spare_size, 4));
  576. break;
  577. default:
  578. dev_err(info->controller.active->mtd.dev,
  579. "%s: invalid state %d\n", __func__, info->state);
  580. BUG();
  581. }
  582. /* Update buffer pointers for multi-page read/write */
  583. info->data_buff_pos += data_len;
  584. info->oob_buff_pos += info->step_spare_size;
  585. }
  586. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  587. {
  588. handle_data_pio(info);
  589. info->state = STATE_CMD_DONE;
  590. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  591. }
  592. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  593. {
  594. unsigned int status, is_completed = 0, is_ready = 0;
  595. unsigned int ready, cmd_done;
  596. irqreturn_t ret = IRQ_HANDLED;
  597. if (info->cs == 0) {
  598. ready = NDSR_FLASH_RDY;
  599. cmd_done = NDSR_CS0_CMDD;
  600. } else {
  601. ready = NDSR_RDY;
  602. cmd_done = NDSR_CS1_CMDD;
  603. }
  604. /* TODO - find out why we need the delay during write operation. */
  605. ndelay(1);
  606. status = nand_readl(info, NDSR);
  607. if (status & NDSR_UNCORERR)
  608. info->retcode = ERR_UNCORERR;
  609. if (status & NDSR_CORERR) {
  610. info->retcode = ERR_CORERR;
  611. if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
  612. info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
  613. info->ecc_bch)
  614. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  615. else
  616. info->ecc_err_cnt = 1;
  617. /*
  618. * Each chunk composing a page is corrected independently,
  619. * and we need to store maximum number of corrected bitflips
  620. * to return it to the MTD layer in ecc.read_page().
  621. */
  622. info->max_bitflips = max_t(unsigned int,
  623. info->max_bitflips,
  624. info->ecc_err_cnt);
  625. }
  626. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  627. info->state = (status & NDSR_RDDREQ) ?
  628. STATE_PIO_READING : STATE_PIO_WRITING;
  629. /* Call the IRQ thread in U-Boot directly */
  630. pxa3xx_nand_irq_thread(info);
  631. return 0;
  632. }
  633. if (status & cmd_done) {
  634. info->state = STATE_CMD_DONE;
  635. is_completed = 1;
  636. }
  637. if (status & ready) {
  638. info->state = STATE_READY;
  639. is_ready = 1;
  640. }
  641. /*
  642. * Clear all status bit before issuing the next command, which
  643. * can and will alter the status bits and will deserve a new
  644. * interrupt on its own. This lets the controller exit the IRQ
  645. */
  646. nand_writel(info, NDSR, status);
  647. if (status & NDSR_WRCMDREQ) {
  648. status &= ~NDSR_WRCMDREQ;
  649. info->state = STATE_CMD_HANDLE;
  650. /*
  651. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  652. * must be loaded by writing directly either 12 or 16
  653. * bytes directly to NDCB0, four bytes at a time.
  654. *
  655. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  656. * but each NDCBx register can be read.
  657. */
  658. nand_writel(info, NDCB0, info->ndcb0);
  659. nand_writel(info, NDCB0, info->ndcb1);
  660. nand_writel(info, NDCB0, info->ndcb2);
  661. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  662. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
  663. info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
  664. nand_writel(info, NDCB0, info->ndcb3);
  665. }
  666. if (is_completed)
  667. info->cmd_complete = 1;
  668. if (is_ready)
  669. info->dev_ready = 1;
  670. return ret;
  671. }
  672. static inline int is_buf_blank(uint8_t *buf, size_t len)
  673. {
  674. for (; len > 0; len--)
  675. if (*buf++ != 0xff)
  676. return 0;
  677. return 1;
  678. }
  679. static void set_command_address(struct pxa3xx_nand_info *info,
  680. unsigned int page_size, uint16_t column, int page_addr)
  681. {
  682. /* small page addr setting */
  683. if (page_size < info->chunk_size) {
  684. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  685. | (column & 0xFF);
  686. info->ndcb2 = 0;
  687. } else {
  688. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  689. | (column & 0xFFFF);
  690. if (page_addr & 0xFF0000)
  691. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  692. else
  693. info->ndcb2 = 0;
  694. }
  695. }
  696. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  697. {
  698. struct pxa3xx_nand_host *host = info->host[info->cs];
  699. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  700. /* reset data and oob column point to handle data */
  701. info->buf_start = 0;
  702. info->buf_count = 0;
  703. info->data_buff_pos = 0;
  704. info->oob_buff_pos = 0;
  705. info->step_chunk_size = 0;
  706. info->step_spare_size = 0;
  707. info->cur_chunk = 0;
  708. info->use_ecc = 0;
  709. info->use_spare = 1;
  710. info->retcode = ERR_NONE;
  711. info->ecc_err_cnt = 0;
  712. info->ndcb3 = 0;
  713. info->need_wait = 0;
  714. switch (command) {
  715. case NAND_CMD_READ0:
  716. case NAND_CMD_READOOB:
  717. case NAND_CMD_PAGEPROG:
  718. if (!info->force_raw)
  719. info->use_ecc = 1;
  720. break;
  721. case NAND_CMD_PARAM:
  722. info->use_spare = 0;
  723. break;
  724. default:
  725. info->ndcb1 = 0;
  726. info->ndcb2 = 0;
  727. break;
  728. }
  729. /*
  730. * If we are about to issue a read command, or about to set
  731. * the write address, then clean the data buffer.
  732. */
  733. if (command == NAND_CMD_READ0 ||
  734. command == NAND_CMD_READOOB ||
  735. command == NAND_CMD_SEQIN) {
  736. info->buf_count = mtd->writesize + mtd->oobsize;
  737. memset(info->data_buff, 0xFF, info->buf_count);
  738. }
  739. }
  740. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  741. int ext_cmd_type, uint16_t column, int page_addr)
  742. {
  743. int addr_cycle, exec_cmd;
  744. struct pxa3xx_nand_host *host;
  745. struct mtd_info *mtd;
  746. host = info->host[info->cs];
  747. mtd = nand_to_mtd(&host->chip);
  748. addr_cycle = 0;
  749. exec_cmd = 1;
  750. if (info->cs != 0)
  751. info->ndcb0 = NDCB0_CSEL;
  752. else
  753. info->ndcb0 = 0;
  754. if (command == NAND_CMD_SEQIN)
  755. exec_cmd = 0;
  756. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  757. + host->col_addr_cycles);
  758. switch (command) {
  759. case NAND_CMD_READOOB:
  760. case NAND_CMD_READ0:
  761. info->buf_start = column;
  762. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  763. | addr_cycle
  764. | NAND_CMD_READ0;
  765. if (command == NAND_CMD_READOOB)
  766. info->buf_start += mtd->writesize;
  767. if (info->cur_chunk < info->nfullchunks) {
  768. info->step_chunk_size = info->chunk_size;
  769. info->step_spare_size = info->spare_size;
  770. } else {
  771. info->step_chunk_size = info->last_chunk_size;
  772. info->step_spare_size = info->last_spare_size;
  773. }
  774. /*
  775. * Multiple page read needs an 'extended command type' field,
  776. * which is either naked-read or last-read according to the
  777. * state.
  778. */
  779. if (info->force_raw) {
  780. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) |
  781. NDCB0_LEN_OVRD |
  782. NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  783. info->ndcb3 = info->step_chunk_size +
  784. info->step_spare_size + info->ecc_size;
  785. } else if (mtd->writesize == info->chunk_size) {
  786. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  787. } else if (mtd->writesize > info->chunk_size) {
  788. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  789. | NDCB0_LEN_OVRD
  790. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  791. info->ndcb3 = info->step_chunk_size +
  792. info->step_spare_size;
  793. }
  794. set_command_address(info, mtd->writesize, column, page_addr);
  795. break;
  796. case NAND_CMD_SEQIN:
  797. info->buf_start = column;
  798. set_command_address(info, mtd->writesize, 0, page_addr);
  799. /*
  800. * Multiple page programming needs to execute the initial
  801. * SEQIN command that sets the page address.
  802. */
  803. if (mtd->writesize > info->chunk_size) {
  804. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  805. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  806. | addr_cycle
  807. | command;
  808. exec_cmd = 1;
  809. }
  810. break;
  811. case NAND_CMD_PAGEPROG:
  812. if (is_buf_blank(info->data_buff,
  813. (mtd->writesize + mtd->oobsize))) {
  814. exec_cmd = 0;
  815. break;
  816. }
  817. if (info->cur_chunk < info->nfullchunks) {
  818. info->step_chunk_size = info->chunk_size;
  819. info->step_spare_size = info->spare_size;
  820. } else {
  821. info->step_chunk_size = info->last_chunk_size;
  822. info->step_spare_size = info->last_spare_size;
  823. }
  824. /* Second command setting for large pages */
  825. if (mtd->writesize > info->chunk_size) {
  826. /*
  827. * Multiple page write uses the 'extended command'
  828. * field. This can be used to issue a command dispatch
  829. * or a naked-write depending on the current stage.
  830. */
  831. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  832. | NDCB0_LEN_OVRD
  833. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  834. info->ndcb3 = info->step_chunk_size +
  835. info->step_spare_size;
  836. /*
  837. * This is the command dispatch that completes a chunked
  838. * page program operation.
  839. */
  840. if (info->cur_chunk == info->ntotalchunks) {
  841. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  842. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  843. | command;
  844. info->ndcb1 = 0;
  845. info->ndcb2 = 0;
  846. info->ndcb3 = 0;
  847. }
  848. } else {
  849. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  850. | NDCB0_AUTO_RS
  851. | NDCB0_ST_ROW_EN
  852. | NDCB0_DBC
  853. | (NAND_CMD_PAGEPROG << 8)
  854. | NAND_CMD_SEQIN
  855. | addr_cycle;
  856. }
  857. break;
  858. case NAND_CMD_PARAM:
  859. info->buf_count = INIT_BUFFER_SIZE;
  860. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  861. | NDCB0_ADDR_CYC(1)
  862. | NDCB0_LEN_OVRD
  863. | command;
  864. info->ndcb1 = (column & 0xFF);
  865. info->ndcb3 = INIT_BUFFER_SIZE;
  866. info->step_chunk_size = INIT_BUFFER_SIZE;
  867. break;
  868. case NAND_CMD_READID:
  869. info->buf_count = READ_ID_BYTES;
  870. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  871. | NDCB0_ADDR_CYC(1)
  872. | command;
  873. info->ndcb1 = (column & 0xFF);
  874. info->step_chunk_size = 8;
  875. break;
  876. case NAND_CMD_STATUS:
  877. info->buf_count = 1;
  878. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  879. | NDCB0_ADDR_CYC(1)
  880. | command;
  881. info->step_chunk_size = 8;
  882. break;
  883. case NAND_CMD_ERASE1:
  884. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  885. | NDCB0_AUTO_RS
  886. | NDCB0_ADDR_CYC(3)
  887. | NDCB0_DBC
  888. | (NAND_CMD_ERASE2 << 8)
  889. | NAND_CMD_ERASE1;
  890. info->ndcb1 = page_addr;
  891. info->ndcb2 = 0;
  892. break;
  893. case NAND_CMD_RESET:
  894. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  895. | command;
  896. break;
  897. case NAND_CMD_ERASE2:
  898. exec_cmd = 0;
  899. break;
  900. default:
  901. exec_cmd = 0;
  902. dev_err(mtd->dev, "non-supported command %x\n",
  903. command);
  904. break;
  905. }
  906. return exec_cmd;
  907. }
  908. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  909. int column, int page_addr)
  910. {
  911. struct nand_chip *chip = mtd_to_nand(mtd);
  912. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  913. struct pxa3xx_nand_info *info = host->info_data;
  914. int exec_cmd;
  915. /*
  916. * if this is a x16 device ,then convert the input
  917. * "byte" address into a "word" address appropriate
  918. * for indexing a word-oriented device
  919. */
  920. if (info->reg_ndcr & NDCR_DWIDTH_M)
  921. column /= 2;
  922. /*
  923. * There may be different NAND chip hooked to
  924. * different chip select, so check whether
  925. * chip select has been changed, if yes, reset the timing
  926. */
  927. if (info->cs != host->cs) {
  928. info->cs = host->cs;
  929. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  930. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  931. }
  932. prepare_start_command(info, command);
  933. info->state = STATE_PREPARED;
  934. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  935. if (exec_cmd) {
  936. u32 ts;
  937. info->cmd_complete = 0;
  938. info->dev_ready = 0;
  939. info->need_wait = 1;
  940. pxa3xx_nand_start(info);
  941. ts = get_timer(0);
  942. while (1) {
  943. u32 status;
  944. status = nand_readl(info, NDSR);
  945. if (status)
  946. pxa3xx_nand_irq(info);
  947. if (info->cmd_complete)
  948. break;
  949. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  950. dev_err(mtd->dev, "Wait timeout!!!\n");
  951. return;
  952. }
  953. }
  954. }
  955. info->state = STATE_IDLE;
  956. }
  957. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  958. const unsigned command,
  959. int column, int page_addr)
  960. {
  961. struct nand_chip *chip = mtd_to_nand(mtd);
  962. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  963. struct pxa3xx_nand_info *info = host->info_data;
  964. int exec_cmd, ext_cmd_type;
  965. /*
  966. * if this is a x16 device then convert the input
  967. * "byte" address into a "word" address appropriate
  968. * for indexing a word-oriented device
  969. */
  970. if (info->reg_ndcr & NDCR_DWIDTH_M)
  971. column /= 2;
  972. /*
  973. * There may be different NAND chip hooked to
  974. * different chip select, so check whether
  975. * chip select has been changed, if yes, reset the timing
  976. */
  977. if (info->cs != host->cs) {
  978. info->cs = host->cs;
  979. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  980. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  981. }
  982. /* Select the extended command for the first command */
  983. switch (command) {
  984. case NAND_CMD_READ0:
  985. case NAND_CMD_READOOB:
  986. ext_cmd_type = EXT_CMD_TYPE_MONO;
  987. break;
  988. case NAND_CMD_SEQIN:
  989. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  990. break;
  991. case NAND_CMD_PAGEPROG:
  992. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  993. break;
  994. default:
  995. ext_cmd_type = 0;
  996. break;
  997. }
  998. prepare_start_command(info, command);
  999. /*
  1000. * Prepare the "is ready" completion before starting a command
  1001. * transaction sequence. If the command is not executed the
  1002. * completion will be completed, see below.
  1003. *
  1004. * We can do that inside the loop because the command variable
  1005. * is invariant and thus so is the exec_cmd.
  1006. */
  1007. info->need_wait = 1;
  1008. info->dev_ready = 0;
  1009. do {
  1010. u32 ts;
  1011. info->state = STATE_PREPARED;
  1012. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  1013. column, page_addr);
  1014. if (!exec_cmd) {
  1015. info->need_wait = 0;
  1016. info->dev_ready = 1;
  1017. break;
  1018. }
  1019. info->cmd_complete = 0;
  1020. pxa3xx_nand_start(info);
  1021. ts = get_timer(0);
  1022. while (1) {
  1023. u32 status;
  1024. status = nand_readl(info, NDSR);
  1025. if (status)
  1026. pxa3xx_nand_irq(info);
  1027. if (info->cmd_complete)
  1028. break;
  1029. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1030. dev_err(mtd->dev, "Wait timeout!!!\n");
  1031. return;
  1032. }
  1033. }
  1034. /* Only a few commands need several steps */
  1035. if (command != NAND_CMD_PAGEPROG &&
  1036. command != NAND_CMD_READ0 &&
  1037. command != NAND_CMD_READOOB)
  1038. break;
  1039. info->cur_chunk++;
  1040. /* Check if the sequence is complete */
  1041. if (info->cur_chunk == info->ntotalchunks &&
  1042. command != NAND_CMD_PAGEPROG)
  1043. break;
  1044. /*
  1045. * After a splitted program command sequence has issued
  1046. * the command dispatch, the command sequence is complete.
  1047. */
  1048. if (info->cur_chunk == (info->ntotalchunks + 1) &&
  1049. command == NAND_CMD_PAGEPROG &&
  1050. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  1051. break;
  1052. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  1053. /* Last read: issue a 'last naked read' */
  1054. if (info->cur_chunk == info->ntotalchunks - 1)
  1055. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  1056. else
  1057. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  1058. /*
  1059. * If a splitted program command has no more data to transfer,
  1060. * the command dispatch must be issued to complete.
  1061. */
  1062. } else if (command == NAND_CMD_PAGEPROG &&
  1063. info->cur_chunk == info->ntotalchunks) {
  1064. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  1065. }
  1066. } while (1);
  1067. info->state = STATE_IDLE;
  1068. }
  1069. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  1070. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  1071. int page)
  1072. {
  1073. chip->write_buf(mtd, buf, mtd->writesize);
  1074. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1075. return 0;
  1076. }
  1077. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  1078. struct nand_chip *chip, uint8_t *buf, int oob_required,
  1079. int page)
  1080. {
  1081. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1082. struct pxa3xx_nand_info *info = host->info_data;
  1083. int bf;
  1084. chip->read_buf(mtd, buf, mtd->writesize);
  1085. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1086. if (info->retcode == ERR_CORERR && info->use_ecc) {
  1087. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  1088. } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) {
  1089. /*
  1090. * Empty pages will trigger uncorrectable errors. Re-read the
  1091. * entire page in raw mode and check for bits not being "1".
  1092. * If there are more than the supported strength, then it means
  1093. * this is an actual uncorrectable error.
  1094. */
  1095. chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page);
  1096. bf = nand_check_erased_ecc_chunk(buf, mtd->writesize,
  1097. chip->oob_poi, mtd->oobsize,
  1098. NULL, 0, chip->ecc.strength);
  1099. if (bf < 0) {
  1100. mtd->ecc_stats.failed++;
  1101. } else if (bf) {
  1102. mtd->ecc_stats.corrected += bf;
  1103. info->max_bitflips = max_t(unsigned int,
  1104. info->max_bitflips, bf);
  1105. info->retcode = ERR_CORERR;
  1106. } else {
  1107. info->retcode = ERR_NONE;
  1108. }
  1109. } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) {
  1110. /* Raw read is not supported with Hamming ECC engine */
  1111. if (is_buf_blank(buf, mtd->writesize))
  1112. info->retcode = ERR_NONE;
  1113. else
  1114. mtd->ecc_stats.failed++;
  1115. }
  1116. return info->max_bitflips;
  1117. }
  1118. static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd,
  1119. struct nand_chip *chip, uint8_t *buf,
  1120. int oob_required, int page)
  1121. {
  1122. struct pxa3xx_nand_host *host = chip->priv;
  1123. struct pxa3xx_nand_info *info = host->info_data;
  1124. int chunk, ecc_off_buf;
  1125. if (!info->ecc_bch)
  1126. return -ENOTSUPP;
  1127. /*
  1128. * Set the force_raw boolean, then re-call ->cmdfunc() that will run
  1129. * pxa3xx_nand_start(), which will actually disable the ECC engine.
  1130. */
  1131. info->force_raw = true;
  1132. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1133. ecc_off_buf = (info->nfullchunks * info->spare_size) +
  1134. info->last_spare_size;
  1135. for (chunk = 0; chunk < info->nfullchunks; chunk++) {
  1136. chip->read_buf(mtd,
  1137. buf + (chunk * info->chunk_size),
  1138. info->chunk_size);
  1139. chip->read_buf(mtd,
  1140. chip->oob_poi +
  1141. (chunk * (info->spare_size)),
  1142. info->spare_size);
  1143. chip->read_buf(mtd,
  1144. chip->oob_poi + ecc_off_buf +
  1145. (chunk * (info->ecc_size)),
  1146. info->ecc_size - 2);
  1147. }
  1148. if (info->ntotalchunks > info->nfullchunks) {
  1149. chip->read_buf(mtd,
  1150. buf + (info->nfullchunks * info->chunk_size),
  1151. info->last_chunk_size);
  1152. chip->read_buf(mtd,
  1153. chip->oob_poi +
  1154. (info->nfullchunks * (info->spare_size)),
  1155. info->last_spare_size);
  1156. chip->read_buf(mtd,
  1157. chip->oob_poi + ecc_off_buf +
  1158. (info->nfullchunks * (info->ecc_size)),
  1159. info->ecc_size - 2);
  1160. }
  1161. info->force_raw = false;
  1162. return 0;
  1163. }
  1164. static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd,
  1165. struct nand_chip *chip, int page)
  1166. {
  1167. /* Invalidate page cache */
  1168. chip->pagebuf = -1;
  1169. return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true,
  1170. page);
  1171. }
  1172. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  1173. {
  1174. struct nand_chip *chip = mtd_to_nand(mtd);
  1175. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1176. struct pxa3xx_nand_info *info = host->info_data;
  1177. char retval = 0xFF;
  1178. if (info->buf_start < info->buf_count)
  1179. /* Has just send a new command? */
  1180. retval = info->data_buff[info->buf_start++];
  1181. return retval;
  1182. }
  1183. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  1184. {
  1185. struct nand_chip *chip = mtd_to_nand(mtd);
  1186. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1187. struct pxa3xx_nand_info *info = host->info_data;
  1188. u16 retval = 0xFFFF;
  1189. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  1190. retval = *((u16 *)(info->data_buff+info->buf_start));
  1191. info->buf_start += 2;
  1192. }
  1193. return retval;
  1194. }
  1195. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1196. {
  1197. struct nand_chip *chip = mtd_to_nand(mtd);
  1198. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1199. struct pxa3xx_nand_info *info = host->info_data;
  1200. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1201. memcpy(buf, info->data_buff + info->buf_start, real_len);
  1202. info->buf_start += real_len;
  1203. }
  1204. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  1205. const uint8_t *buf, int len)
  1206. {
  1207. struct nand_chip *chip = mtd_to_nand(mtd);
  1208. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1209. struct pxa3xx_nand_info *info = host->info_data;
  1210. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1211. memcpy(info->data_buff + info->buf_start, buf, real_len);
  1212. info->buf_start += real_len;
  1213. }
  1214. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  1215. {
  1216. return;
  1217. }
  1218. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1219. {
  1220. struct nand_chip *chip = mtd_to_nand(mtd);
  1221. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1222. struct pxa3xx_nand_info *info = host->info_data;
  1223. if (info->need_wait) {
  1224. u32 ts;
  1225. info->need_wait = 0;
  1226. ts = get_timer(0);
  1227. while (1) {
  1228. u32 status;
  1229. status = nand_readl(info, NDSR);
  1230. if (status)
  1231. pxa3xx_nand_irq(info);
  1232. if (info->dev_ready)
  1233. break;
  1234. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1235. dev_err(mtd->dev, "Ready timeout!!!\n");
  1236. return NAND_STATUS_FAIL;
  1237. }
  1238. }
  1239. }
  1240. /* pxa3xx_nand_send_command has waited for command complete */
  1241. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1242. if (info->retcode == ERR_NONE)
  1243. return 0;
  1244. else
  1245. return NAND_STATUS_FAIL;
  1246. }
  1247. return NAND_STATUS_READY;
  1248. }
  1249. static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
  1250. {
  1251. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1252. /* Configure default flash values */
  1253. info->reg_ndcr = 0x0; /* enable all interrupts */
  1254. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1255. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1256. info->reg_ndcr |= NDCR_SPARE_EN;
  1257. return 0;
  1258. }
  1259. static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
  1260. {
  1261. struct pxa3xx_nand_host *host = info->host[info->cs];
  1262. struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1263. struct nand_chip *chip = mtd_to_nand(mtd);
  1264. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1265. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1266. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1267. }
  1268. static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1269. {
  1270. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1271. uint32_t ndcr = nand_readl(info, NDCR);
  1272. /* Set an initial chunk size */
  1273. info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
  1274. info->reg_ndcr = ndcr &
  1275. ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
  1276. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1277. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1278. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1279. }
  1280. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1281. {
  1282. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1283. if (info->data_buff == NULL)
  1284. return -ENOMEM;
  1285. return 0;
  1286. }
  1287. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1288. {
  1289. struct pxa3xx_nand_info *info = host->info_data;
  1290. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1291. struct mtd_info *mtd;
  1292. struct nand_chip *chip;
  1293. const struct nand_sdr_timings *timings;
  1294. int ret;
  1295. mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1296. chip = mtd_to_nand(mtd);
  1297. /* configure default flash values */
  1298. info->reg_ndcr = 0x0; /* enable all interrupts */
  1299. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1300. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1301. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1302. /* use the common timing to make a try */
  1303. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1304. if (IS_ERR(timings))
  1305. return PTR_ERR(timings);
  1306. pxa3xx_nand_set_sdr_timing(host, timings);
  1307. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1308. ret = chip->waitfunc(mtd, chip);
  1309. if (ret & NAND_STATUS_FAIL)
  1310. return -ENODEV;
  1311. return 0;
  1312. }
  1313. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1314. struct nand_ecc_ctrl *ecc,
  1315. int strength, int ecc_stepsize, int page_size)
  1316. {
  1317. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1318. info->nfullchunks = 1;
  1319. info->ntotalchunks = 1;
  1320. info->chunk_size = 2048;
  1321. info->spare_size = 40;
  1322. info->ecc_size = 24;
  1323. ecc->mode = NAND_ECC_HW;
  1324. ecc->size = 512;
  1325. ecc->strength = 1;
  1326. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1327. info->nfullchunks = 1;
  1328. info->ntotalchunks = 1;
  1329. info->chunk_size = 512;
  1330. info->spare_size = 8;
  1331. info->ecc_size = 8;
  1332. ecc->mode = NAND_ECC_HW;
  1333. ecc->size = 512;
  1334. ecc->strength = 1;
  1335. /*
  1336. * Required ECC: 4-bit correction per 512 bytes
  1337. * Select: 16-bit correction per 2048 bytes
  1338. */
  1339. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1340. info->ecc_bch = 1;
  1341. info->nfullchunks = 1;
  1342. info->ntotalchunks = 1;
  1343. info->chunk_size = 2048;
  1344. info->spare_size = 32;
  1345. info->ecc_size = 32;
  1346. ecc->mode = NAND_ECC_HW;
  1347. ecc->size = info->chunk_size;
  1348. ecc->layout = &ecc_layout_2KB_bch4bit;
  1349. ecc->strength = 16;
  1350. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1351. info->ecc_bch = 1;
  1352. info->nfullchunks = 2;
  1353. info->ntotalchunks = 2;
  1354. info->chunk_size = 2048;
  1355. info->spare_size = 32;
  1356. info->ecc_size = 32;
  1357. ecc->mode = NAND_ECC_HW;
  1358. ecc->size = info->chunk_size;
  1359. ecc->layout = &ecc_layout_4KB_bch4bit;
  1360. ecc->strength = 16;
  1361. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
  1362. info->ecc_bch = 1;
  1363. info->nfullchunks = 4;
  1364. info->ntotalchunks = 4;
  1365. info->chunk_size = 2048;
  1366. info->spare_size = 32;
  1367. info->ecc_size = 32;
  1368. ecc->mode = NAND_ECC_HW;
  1369. ecc->size = info->chunk_size;
  1370. ecc->layout = &ecc_layout_8KB_bch4bit;
  1371. ecc->strength = 16;
  1372. /*
  1373. * Required ECC: 8-bit correction per 512 bytes
  1374. * Select: 16-bit correction per 1024 bytes
  1375. */
  1376. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
  1377. info->ecc_bch = 1;
  1378. info->nfullchunks = 1;
  1379. info->ntotalchunks = 2;
  1380. info->chunk_size = 1024;
  1381. info->spare_size = 0;
  1382. info->last_chunk_size = 1024;
  1383. info->last_spare_size = 32;
  1384. info->ecc_size = 32;
  1385. ecc->mode = NAND_ECC_HW;
  1386. ecc->size = info->chunk_size;
  1387. ecc->layout = &ecc_layout_2KB_bch8bit;
  1388. ecc->strength = 16;
  1389. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1390. info->ecc_bch = 1;
  1391. info->nfullchunks = 4;
  1392. info->ntotalchunks = 5;
  1393. info->chunk_size = 1024;
  1394. info->spare_size = 0;
  1395. info->last_chunk_size = 0;
  1396. info->last_spare_size = 64;
  1397. info->ecc_size = 32;
  1398. ecc->mode = NAND_ECC_HW;
  1399. ecc->size = info->chunk_size;
  1400. ecc->layout = &ecc_layout_4KB_bch8bit;
  1401. ecc->strength = 16;
  1402. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
  1403. info->ecc_bch = 1;
  1404. info->nfullchunks = 8;
  1405. info->ntotalchunks = 9;
  1406. info->chunk_size = 1024;
  1407. info->spare_size = 0;
  1408. info->last_chunk_size = 0;
  1409. info->last_spare_size = 160;
  1410. info->ecc_size = 32;
  1411. ecc->mode = NAND_ECC_HW;
  1412. ecc->size = info->chunk_size;
  1413. ecc->layout = &ecc_layout_8KB_bch8bit;
  1414. ecc->strength = 16;
  1415. } else {
  1416. dev_err(info->controller.active->mtd.dev,
  1417. "ECC strength %d at page size %d is not supported\n",
  1418. strength, page_size);
  1419. return -ENODEV;
  1420. }
  1421. return 0;
  1422. }
  1423. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1424. {
  1425. struct nand_chip *chip = mtd_to_nand(mtd);
  1426. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1427. struct pxa3xx_nand_info *info = host->info_data;
  1428. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1429. int ret;
  1430. uint16_t ecc_strength, ecc_step;
  1431. if (pdata->keep_config) {
  1432. pxa3xx_nand_detect_config(info);
  1433. } else {
  1434. ret = pxa3xx_nand_config_ident(info);
  1435. if (ret)
  1436. return ret;
  1437. ret = pxa3xx_nand_sensing(host);
  1438. if (ret) {
  1439. dev_info(mtd->dev, "There is no chip on cs %d!\n",
  1440. info->cs);
  1441. return ret;
  1442. }
  1443. }
  1444. /* Device detection must be done with ECC disabled */
  1445. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
  1446. info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
  1447. nand_writel(info, NDECCCTRL, 0x0);
  1448. if (nand_scan_ident(mtd, 1, NULL))
  1449. return -ENODEV;
  1450. if (!pdata->keep_config) {
  1451. ret = pxa3xx_nand_init_timings(host);
  1452. if (ret) {
  1453. dev_err(mtd->dev,
  1454. "Failed to set timings: %d\n", ret);
  1455. return ret;
  1456. }
  1457. }
  1458. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1459. /*
  1460. * We'll use a bad block table stored in-flash and don't
  1461. * allow writing the bad block marker to the flash.
  1462. */
  1463. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1464. chip->bbt_td = &bbt_main_descr;
  1465. chip->bbt_md = &bbt_mirror_descr;
  1466. #endif
  1467. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1468. ecc_strength = pdata->ecc_strength;
  1469. ecc_step = pdata->ecc_step_size;
  1470. } else {
  1471. ecc_strength = chip->ecc_strength_ds;
  1472. ecc_step = chip->ecc_step_ds;
  1473. }
  1474. /* Set default ECC strength requirements on non-ONFI devices */
  1475. if (ecc_strength < 1 && ecc_step < 1) {
  1476. ecc_strength = 1;
  1477. ecc_step = 512;
  1478. }
  1479. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1480. ecc_step, mtd->writesize);
  1481. if (ret)
  1482. return ret;
  1483. /*
  1484. * If the page size is bigger than the FIFO size, let's check
  1485. * we are given the right variant and then switch to the extended
  1486. * (aka split) command handling,
  1487. */
  1488. if (mtd->writesize > info->chunk_size) {
  1489. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
  1490. info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
  1491. chip->cmdfunc = nand_cmdfunc_extended;
  1492. } else {
  1493. dev_err(mtd->dev,
  1494. "unsupported page size on this variant\n");
  1495. return -ENODEV;
  1496. }
  1497. }
  1498. /* calculate addressing information */
  1499. if (mtd->writesize >= 2048)
  1500. host->col_addr_cycles = 2;
  1501. else
  1502. host->col_addr_cycles = 1;
  1503. /* release the initial buffer */
  1504. kfree(info->data_buff);
  1505. /* allocate the real data + oob buffer */
  1506. info->buf_size = mtd->writesize + mtd->oobsize;
  1507. ret = pxa3xx_nand_init_buff(info);
  1508. if (ret)
  1509. return ret;
  1510. info->oob_buff = info->data_buff + mtd->writesize;
  1511. if ((mtd->size >> chip->page_shift) > 65536)
  1512. host->row_addr_cycles = 3;
  1513. else
  1514. host->row_addr_cycles = 2;
  1515. if (!pdata->keep_config)
  1516. pxa3xx_nand_config_tail(info);
  1517. return nand_scan_tail(mtd);
  1518. }
  1519. static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info)
  1520. {
  1521. struct pxa3xx_nand_platform_data *pdata;
  1522. struct pxa3xx_nand_host *host;
  1523. struct nand_chip *chip = NULL;
  1524. struct mtd_info *mtd;
  1525. int cs;
  1526. pdata = info->pdata;
  1527. if (pdata->num_cs <= 0)
  1528. return -ENODEV;
  1529. info->variant = pxa3xx_nand_get_variant(dev);
  1530. for (cs = 0; cs < pdata->num_cs; cs++) {
  1531. chip = (struct nand_chip *)
  1532. ((u8 *)&info[1] + sizeof(*host) * cs);
  1533. mtd = nand_to_mtd(chip);
  1534. host = (struct pxa3xx_nand_host *)chip;
  1535. info->host[cs] = host;
  1536. host->cs = cs;
  1537. host->info_data = info;
  1538. mtd->owner = THIS_MODULE;
  1539. nand_set_controller_data(chip, host);
  1540. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1541. chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw;
  1542. chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw;
  1543. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1544. chip->controller = &info->controller;
  1545. chip->waitfunc = pxa3xx_nand_waitfunc;
  1546. chip->select_chip = pxa3xx_nand_select_chip;
  1547. chip->read_word = pxa3xx_nand_read_word;
  1548. chip->read_byte = pxa3xx_nand_read_byte;
  1549. chip->read_buf = pxa3xx_nand_read_buf;
  1550. chip->write_buf = pxa3xx_nand_write_buf;
  1551. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1552. chip->cmdfunc = nand_cmdfunc;
  1553. }
  1554. /* Allocate a buffer to allow flash detection */
  1555. info->buf_size = INIT_BUFFER_SIZE;
  1556. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1557. if (info->data_buff == NULL)
  1558. return -ENOMEM;
  1559. /* initialize all interrupts to be disabled */
  1560. disable_int(info, NDSR_MASK);
  1561. /*
  1562. * Some SoCs like A7k/A8k need to enable manually the NAND
  1563. * controller to avoid being bootloader dependent. This is done
  1564. * through the use of a single bit in the System Functions registers.
  1565. */
  1566. if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
  1567. struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
  1568. dev, "marvell,system-controller");
  1569. u32 reg;
  1570. if (IS_ERR(sysctrl_base))
  1571. return PTR_ERR(sysctrl_base);
  1572. regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
  1573. reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
  1574. regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
  1575. }
  1576. return 0;
  1577. }
  1578. static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info)
  1579. {
  1580. struct pxa3xx_nand_platform_data *pdata;
  1581. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1582. if (!pdata)
  1583. return -ENOMEM;
  1584. info->mmio_base = dev_read_addr_ptr(dev);
  1585. pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1);
  1586. if (pdata->num_cs != 1) {
  1587. pr_err("pxa3xx driver supports single CS only\n");
  1588. return -EINVAL;
  1589. }
  1590. if (dev_read_bool(dev, "nand-enable-arbiter"))
  1591. pdata->enable_arbiter = 1;
  1592. if (dev_read_bool(dev, "nand-keep-config"))
  1593. pdata->keep_config = 1;
  1594. /*
  1595. * ECC parameters.
  1596. * If these are not set, they will be selected according
  1597. * to the detected flash type.
  1598. */
  1599. /* ECC strength */
  1600. pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0);
  1601. /* ECC step size */
  1602. pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size",
  1603. 0);
  1604. info->pdata = pdata;
  1605. return 0;
  1606. }
  1607. static int pxa3xx_nand_probe(struct udevice *dev)
  1608. {
  1609. struct pxa3xx_nand_platform_data *pdata;
  1610. int ret, cs, probe_success;
  1611. struct pxa3xx_nand_info *info = dev_get_priv(dev);
  1612. ret = pxa3xx_nand_probe_dt(dev, info);
  1613. if (ret)
  1614. return ret;
  1615. pdata = info->pdata;
  1616. ret = alloc_nand_resource(dev, info);
  1617. if (ret) {
  1618. dev_err(dev, "alloc nand resource failed\n");
  1619. return ret;
  1620. }
  1621. probe_success = 0;
  1622. for (cs = 0; cs < pdata->num_cs; cs++) {
  1623. struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
  1624. /*
  1625. * The mtd name matches the one used in 'mtdparts' kernel
  1626. * parameter. This name cannot be changed or otherwise
  1627. * user's mtd partitions configuration would get broken.
  1628. */
  1629. mtd->name = "pxa3xx_nand-0";
  1630. info->cs = cs;
  1631. ret = pxa3xx_nand_scan(mtd);
  1632. if (ret) {
  1633. dev_info(mtd->dev, "failed to scan nand at cs %d\n",
  1634. cs);
  1635. continue;
  1636. }
  1637. if (nand_register(cs, mtd))
  1638. continue;
  1639. probe_success = 1;
  1640. }
  1641. if (!probe_success)
  1642. return -ENODEV;
  1643. return 0;
  1644. }
  1645. U_BOOT_DRIVER(pxa3xx_nand) = {
  1646. .name = "pxa3xx-nand",
  1647. .id = UCLASS_MTD,
  1648. .of_match = pxa3xx_nand_dt_ids,
  1649. .probe = pxa3xx_nand_probe,
  1650. .priv_auto = sizeof(struct pxa3xx_nand_info) +
  1651. sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1652. };
  1653. void board_nand_init(void)
  1654. {
  1655. struct udevice *dev;
  1656. int ret;
  1657. ret = uclass_get_device_by_driver(UCLASS_MTD,
  1658. DM_DRIVER_GET(pxa3xx_nand), &dev);
  1659. if (ret && ret != -ENODEV) {
  1660. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  1661. ret);
  1662. }
  1663. }