davinci_nand.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NAND driver for TI DaVinci based boards.
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. *
  7. * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
  8. */
  9. /*
  10. *
  11. * linux/drivers/mtd/nand/raw/nand_davinci.c
  12. *
  13. * NAND Flash Driver
  14. *
  15. * Copyright (C) 2006 Texas Instruments.
  16. *
  17. * ----------------------------------------------------------------------------
  18. *
  19. * ----------------------------------------------------------------------------
  20. *
  21. * Overview:
  22. * This is a device driver for the NAND flash device found on the
  23. * DaVinci board which utilizes the Samsung k9k2g08 part.
  24. *
  25. Modifications:
  26. ver. 1.0: Feb 2005, Vinod/Sudhakar
  27. -
  28. */
  29. #include <common.h>
  30. #include <log.h>
  31. #include <asm/io.h>
  32. #include <nand.h>
  33. #include <dm/uclass.h>
  34. #include <asm/ti-common/davinci_nand.h>
  35. /* Definitions for 4-bit hardware ECC */
  36. #define NAND_TIMEOUT 10240
  37. #define NAND_ECC_BUSY 0xC
  38. #define NAND_4BITECC_MASK 0x03FF03FF
  39. #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
  40. #define ECC_STATE_NO_ERR 0x0
  41. #define ECC_STATE_TOO_MANY_ERRS 0x1
  42. #define ECC_STATE_ERR_CORR_COMP_P 0x2
  43. #define ECC_STATE_ERR_CORR_COMP_N 0x3
  44. /*
  45. * Exploit the little endianness of the ARM to do multi-byte transfers
  46. * per device read. This can perform over twice as quickly as individual
  47. * byte transfers when buffer alignment is conducive.
  48. *
  49. * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  50. * the address bus. On Davinci EVM platforms this has always been true.
  51. */
  52. static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  53. {
  54. struct nand_chip *chip = mtd_to_nand(mtd);
  55. const u32 *nand = chip->IO_ADDR_R;
  56. /* Make sure that buf is 32 bit aligned */
  57. if (((int)buf & 0x3) != 0) {
  58. if (((int)buf & 0x1) != 0) {
  59. if (len) {
  60. *buf = readb(nand);
  61. buf += 1;
  62. len--;
  63. }
  64. }
  65. if (((int)buf & 0x3) != 0) {
  66. if (len >= 2) {
  67. *(u16 *)buf = readw(nand);
  68. buf += 2;
  69. len -= 2;
  70. }
  71. }
  72. }
  73. /* copy aligned data */
  74. while (len >= 4) {
  75. *(u32 *)buf = __raw_readl(nand);
  76. buf += 4;
  77. len -= 4;
  78. }
  79. /* mop up any remaining bytes */
  80. if (len) {
  81. if (len >= 2) {
  82. *(u16 *)buf = readw(nand);
  83. buf += 2;
  84. len -= 2;
  85. }
  86. if (len)
  87. *buf = readb(nand);
  88. }
  89. }
  90. static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  91. int len)
  92. {
  93. struct nand_chip *chip = mtd_to_nand(mtd);
  94. const u32 *nand = chip->IO_ADDR_W;
  95. /* Make sure that buf is 32 bit aligned */
  96. if (((int)buf & 0x3) != 0) {
  97. if (((int)buf & 0x1) != 0) {
  98. if (len) {
  99. writeb(*buf, nand);
  100. buf += 1;
  101. len--;
  102. }
  103. }
  104. if (((int)buf & 0x3) != 0) {
  105. if (len >= 2) {
  106. writew(*(u16 *)buf, nand);
  107. buf += 2;
  108. len -= 2;
  109. }
  110. }
  111. }
  112. /* copy aligned data */
  113. while (len >= 4) {
  114. __raw_writel(*(u32 *)buf, nand);
  115. buf += 4;
  116. len -= 4;
  117. }
  118. /* mop up any remaining bytes */
  119. if (len) {
  120. if (len >= 2) {
  121. writew(*(u16 *)buf, nand);
  122. buf += 2;
  123. len -= 2;
  124. }
  125. if (len)
  126. writeb(*buf, nand);
  127. }
  128. }
  129. static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
  130. unsigned int ctrl)
  131. {
  132. struct nand_chip *this = mtd_to_nand(mtd);
  133. u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
  134. if (ctrl & NAND_CTRL_CHANGE) {
  135. IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
  136. if (ctrl & NAND_CLE)
  137. IO_ADDR_W |= MASK_CLE;
  138. if (ctrl & NAND_ALE)
  139. IO_ADDR_W |= MASK_ALE;
  140. this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
  141. }
  142. if (cmd != NAND_CMD_NONE)
  143. writeb(cmd, IO_ADDR_W);
  144. }
  145. #ifdef CONFIG_SYS_NAND_HW_ECC
  146. static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
  147. {
  148. u_int32_t ecc = 0;
  149. ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
  150. CONFIG_SYS_NAND_CS - 2]));
  151. return ecc;
  152. }
  153. static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
  154. {
  155. u_int32_t val;
  156. /* reading the ECC result register resets the ECC calculation */
  157. nand_davinci_readecc(mtd);
  158. val = __raw_readl(&davinci_emif_regs->nandfcr);
  159. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  160. val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
  161. __raw_writel(val, &davinci_emif_regs->nandfcr);
  162. }
  163. static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  164. u_char *ecc_code)
  165. {
  166. u_int32_t tmp;
  167. tmp = nand_davinci_readecc(mtd);
  168. /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
  169. * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
  170. tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
  171. /* Invert so that erased block ECC is correct */
  172. tmp = ~tmp;
  173. *ecc_code++ = tmp;
  174. *ecc_code++ = tmp >> 8;
  175. *ecc_code++ = tmp >> 16;
  176. /* NOTE: the above code matches mainline Linux:
  177. * .PQR.stu ==> ~PQRstu
  178. *
  179. * MontaVista/TI kernels encode those bytes differently, use
  180. * complicated (and allegedly sometimes-wrong) correction code,
  181. * and usually shipped with U-Boot that uses software ECC:
  182. * .PQR.stu ==> PsQRtu
  183. *
  184. * If you need MV/TI compatible NAND I/O in U-Boot, it should
  185. * be possible to (a) change the mangling above, (b) reverse
  186. * that mangling in nand_davinci_correct_data() below.
  187. */
  188. return 0;
  189. }
  190. static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
  191. u_char *read_ecc, u_char *calc_ecc)
  192. {
  193. struct nand_chip *this = mtd_to_nand(mtd);
  194. u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
  195. (read_ecc[2] << 16);
  196. u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
  197. (calc_ecc[2] << 16);
  198. u_int32_t diff = ecc_calc ^ ecc_nand;
  199. if (diff) {
  200. if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
  201. /* Correctable error */
  202. if ((diff >> (12 + 3)) < this->ecc.size) {
  203. uint8_t find_bit = 1 << ((diff >> 12) & 7);
  204. uint32_t find_byte = diff >> (12 + 3);
  205. dat[find_byte] ^= find_bit;
  206. pr_debug("Correcting single "
  207. "bit ECC error at offset: %d, bit: "
  208. "%d\n", find_byte, find_bit);
  209. return 1;
  210. } else {
  211. return -EBADMSG;
  212. }
  213. } else if (!(diff & (diff - 1))) {
  214. /* Single bit ECC error in the ECC itself,
  215. nothing to fix */
  216. pr_debug("Single bit ECC error in " "ECC.\n");
  217. return 1;
  218. } else {
  219. /* Uncorrectable error */
  220. pr_debug("ECC UNCORRECTED_ERROR 1\n");
  221. return -EBADMSG;
  222. }
  223. }
  224. return 0;
  225. }
  226. #endif /* CONFIG_SYS_NAND_HW_ECC */
  227. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  228. static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
  229. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  230. .eccbytes = 40,
  231. #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  232. .eccpos = {
  233. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  234. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  235. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  236. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  237. },
  238. .oobfree = {
  239. {2, 4}, {16, 6}, {32, 6}, {48, 6},
  240. },
  241. #else
  242. .eccpos = {
  243. 24, 25, 26, 27, 28,
  244. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
  245. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
  246. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
  247. 59, 60, 61, 62, 63,
  248. },
  249. .oobfree = {
  250. {.offset = 2, .length = 22, },
  251. },
  252. #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
  253. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  254. .eccbytes = 80,
  255. .eccpos = {
  256. 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
  257. 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
  258. 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
  259. 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
  260. 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
  261. 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
  262. 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
  263. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  264. },
  265. .oobfree = {
  266. {.offset = 2, .length = 46, },
  267. },
  268. #endif
  269. };
  270. #if defined CONFIG_KEYSTONE_RBL_NAND
  271. static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
  272. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  273. .eccbytes = 40,
  274. .eccpos = {
  275. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  276. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  277. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  278. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  279. },
  280. .oobfree = {
  281. {.offset = 2, .length = 4, },
  282. {.offset = 16, .length = 6, },
  283. {.offset = 32, .length = 6, },
  284. {.offset = 48, .length = 6, },
  285. },
  286. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  287. .eccbytes = 80,
  288. .eccpos = {
  289. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  290. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  291. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  292. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  293. 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
  294. 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
  295. 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
  296. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  297. },
  298. .oobfree = {
  299. {.offset = 2, .length = 4, },
  300. {.offset = 16, .length = 6, },
  301. {.offset = 32, .length = 6, },
  302. {.offset = 48, .length = 6, },
  303. {.offset = 64, .length = 6, },
  304. {.offset = 80, .length = 6, },
  305. {.offset = 96, .length = 6, },
  306. {.offset = 112, .length = 6, },
  307. },
  308. #endif
  309. };
  310. #ifdef CONFIG_SYS_NAND_PAGE_2K
  311. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
  312. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  313. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
  314. #endif
  315. /**
  316. * nand_davinci_write_page - write one page
  317. * @mtd: MTD device structure
  318. * @chip: NAND chip descriptor
  319. * @buf: the data to write
  320. * @oob_required: must write chip->oob_poi to OOB
  321. * @page: page number to write
  322. * @raw: use _raw version of write_page
  323. */
  324. static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  325. uint32_t offset, int data_len,
  326. const uint8_t *buf, int oob_required,
  327. int page, int raw)
  328. {
  329. int status;
  330. int ret = 0;
  331. struct nand_ecclayout *saved_ecc_layout;
  332. /* save current ECC layout and assign Keystone RBL ECC layout */
  333. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  334. saved_ecc_layout = chip->ecc.layout;
  335. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  336. mtd->oobavail = chip->ecc.layout->oobavail;
  337. }
  338. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  339. if (unlikely(raw)) {
  340. status = chip->ecc.write_page_raw(mtd, chip, buf,
  341. oob_required, page);
  342. } else {
  343. status = chip->ecc.write_page(mtd, chip, buf,
  344. oob_required, page);
  345. }
  346. if (status < 0) {
  347. ret = status;
  348. goto err;
  349. }
  350. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  351. status = chip->waitfunc(mtd, chip);
  352. if (status & NAND_STATUS_FAIL) {
  353. ret = -EIO;
  354. goto err;
  355. }
  356. err:
  357. /* restore ECC layout */
  358. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  359. chip->ecc.layout = saved_ecc_layout;
  360. mtd->oobavail = saved_ecc_layout->oobavail;
  361. }
  362. return ret;
  363. }
  364. /**
  365. * nand_davinci_read_page_hwecc - hardware ECC based page read function
  366. * @mtd: mtd info structure
  367. * @chip: nand chip info structure
  368. * @buf: buffer to store read data
  369. * @oob_required: caller requires OOB data read to chip->oob_poi
  370. * @page: page number to read
  371. *
  372. * Not for syndrome calculating ECC controllers which need a special oob layout.
  373. */
  374. static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  375. uint8_t *buf, int oob_required, int page)
  376. {
  377. int i, eccsize = chip->ecc.size;
  378. int eccbytes = chip->ecc.bytes;
  379. int eccsteps = chip->ecc.steps;
  380. uint32_t *eccpos;
  381. uint8_t *p = buf;
  382. uint8_t *ecc_code = chip->buffers->ecccode;
  383. uint8_t *ecc_calc = chip->buffers->ecccalc;
  384. struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
  385. /* save current ECC layout and assign Keystone RBL ECC layout */
  386. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  387. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  388. mtd->oobavail = chip->ecc.layout->oobavail;
  389. }
  390. eccpos = chip->ecc.layout->eccpos;
  391. /* Read the OOB area first */
  392. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  393. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  394. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  395. for (i = 0; i < chip->ecc.total; i++)
  396. ecc_code[i] = chip->oob_poi[eccpos[i]];
  397. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  398. int stat;
  399. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  400. chip->read_buf(mtd, p, eccsize);
  401. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  402. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  403. if (stat < 0)
  404. mtd->ecc_stats.failed++;
  405. else
  406. mtd->ecc_stats.corrected += stat;
  407. }
  408. /* restore ECC layout */
  409. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  410. chip->ecc.layout = saved_ecc_layout;
  411. mtd->oobavail = saved_ecc_layout->oobavail;
  412. }
  413. return 0;
  414. }
  415. #endif /* CONFIG_KEYSTONE_RBL_NAND */
  416. static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
  417. {
  418. u32 val;
  419. switch (mode) {
  420. case NAND_ECC_WRITE:
  421. case NAND_ECC_READ:
  422. /*
  423. * Start a new ECC calculation for reading or writing 512 bytes
  424. * of data.
  425. */
  426. val = __raw_readl(&davinci_emif_regs->nandfcr);
  427. val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
  428. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  429. val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
  430. val |= DAVINCI_NANDFCR_4BIT_ECC_START;
  431. __raw_writel(val, &davinci_emif_regs->nandfcr);
  432. break;
  433. case NAND_ECC_READSYN:
  434. val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
  435. break;
  436. default:
  437. break;
  438. }
  439. }
  440. static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
  441. {
  442. int i;
  443. for (i = 0; i < 4; i++) {
  444. ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
  445. NAND_4BITECC_MASK;
  446. }
  447. return 0;
  448. }
  449. static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
  450. const uint8_t *dat,
  451. uint8_t *ecc_code)
  452. {
  453. unsigned int hw_4ecc[4];
  454. unsigned int i;
  455. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  456. /*Convert 10 bit ecc value to 8 bit */
  457. for (i = 0; i < 2; i++) {
  458. unsigned int hw_ecc_low = hw_4ecc[i * 2];
  459. unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
  460. /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
  461. *ecc_code++ = hw_ecc_low & 0xFF;
  462. /*
  463. * Take 2 bits as LSB bits from val1 (count1=0) or val5
  464. * (count1=1) and 6 bits from val2 (count1=0) or
  465. * val5 (count1=1)
  466. */
  467. *ecc_code++ =
  468. ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
  469. /*
  470. * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
  471. * 4 bits from val3 (count1=0) or val6 (count1=1)
  472. */
  473. *ecc_code++ =
  474. ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
  475. /*
  476. * Take 6 bits from val3(count1=0) or val6 (count1=1) and
  477. * 2 bits from val4 (count1=0) or val7 (count1=1)
  478. */
  479. *ecc_code++ =
  480. ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
  481. /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
  482. *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
  483. }
  484. return 0;
  485. }
  486. static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
  487. uint8_t *read_ecc, uint8_t *calc_ecc)
  488. {
  489. int i;
  490. unsigned int hw_4ecc[4];
  491. unsigned int iserror;
  492. unsigned short *ecc16;
  493. unsigned int numerrors, erroraddress, errorvalue;
  494. u32 val;
  495. /*
  496. * Check for an ECC where all bytes are 0xFF. If this is the case, we
  497. * will assume we are looking at an erased page and we should ignore
  498. * the ECC.
  499. */
  500. for (i = 0; i < 10; i++) {
  501. if (read_ecc[i] != 0xFF)
  502. break;
  503. }
  504. if (i == 10)
  505. return 0;
  506. /* Convert 8 bit in to 10 bit */
  507. ecc16 = (unsigned short *)&read_ecc[0];
  508. /*
  509. * Write the parity values in the NAND Flash 4-bit ECC Load register.
  510. * Write each parity value one at a time starting from 4bit_ecc_val8
  511. * to 4bit_ecc_val1.
  512. */
  513. /*Take 2 bits from 8th byte and 8 bits from 9th byte */
  514. __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
  515. &davinci_emif_regs->nand4biteccload);
  516. /* Take 4 bits from 7th byte and 6 bits from 8th byte */
  517. __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
  518. &davinci_emif_regs->nand4biteccload);
  519. /* Take 6 bits from 6th byte and 4 bits from 7th byte */
  520. __raw_writel((ecc16[3] >> 2) & 0x3FF,
  521. &davinci_emif_regs->nand4biteccload);
  522. /* Take 8 bits from 5th byte and 2 bits from 6th byte */
  523. __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
  524. &davinci_emif_regs->nand4biteccload);
  525. /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
  526. __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
  527. &davinci_emif_regs->nand4biteccload);
  528. /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
  529. __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
  530. &davinci_emif_regs->nand4biteccload);
  531. /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
  532. __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
  533. &davinci_emif_regs->nand4biteccload);
  534. /* Take 10 bits from 0th and 1st bytes */
  535. __raw_writel((ecc16[0]) & 0x3FF,
  536. &davinci_emif_regs->nand4biteccload);
  537. /*
  538. * Perform a dummy read to the EMIF Revision Code and Status register.
  539. * This is required to ensure time for syndrome calculation after
  540. * writing the ECC values in previous step.
  541. */
  542. val = __raw_readl(&davinci_emif_regs->nandfsr);
  543. /*
  544. * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
  545. * A syndrome value of 0 means no bit errors. If the syndrome is
  546. * non-zero then go further otherwise return.
  547. */
  548. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  549. if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
  550. return 0;
  551. /*
  552. * Clear any previous address calculation by doing a dummy read of an
  553. * error address register.
  554. */
  555. val = __raw_readl(&davinci_emif_regs->nanderradd1);
  556. /*
  557. * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
  558. * register to 1.
  559. */
  560. __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
  561. &davinci_emif_regs->nandfcr);
  562. /*
  563. * Wait for the corr_state field (bits 8 to 11) in the
  564. * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
  565. * Otherwise ECC calculation has not even begun and the next loop might
  566. * fail because of a false positive!
  567. */
  568. i = NAND_TIMEOUT;
  569. do {
  570. val = __raw_readl(&davinci_emif_regs->nandfsr);
  571. val &= 0xc00;
  572. i--;
  573. } while ((i > 0) && !val);
  574. /*
  575. * Wait for the corr_state field (bits 8 to 11) in the
  576. * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
  577. */
  578. i = NAND_TIMEOUT;
  579. do {
  580. val = __raw_readl(&davinci_emif_regs->nandfsr);
  581. val &= 0xc00;
  582. i--;
  583. } while ((i > 0) && val);
  584. iserror = __raw_readl(&davinci_emif_regs->nandfsr);
  585. iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
  586. iserror = iserror >> 8;
  587. /*
  588. * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
  589. * corrected (five or more errors). The number of errors
  590. * calculated (err_num field) differs from the number of errors
  591. * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
  592. * correction complete (errors on bit 8 or 9).
  593. * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
  594. * complete (error exists).
  595. */
  596. if (iserror == ECC_STATE_NO_ERR) {
  597. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  598. return 0;
  599. } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
  600. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  601. return -EBADMSG;
  602. }
  603. numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
  604. & 0x3) + 1;
  605. /* Read the error address, error value and correct */
  606. for (i = 0; i < numerrors; i++) {
  607. if (i > 1) {
  608. erroraddress =
  609. ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
  610. (16 * (i & 1))) & 0x3FF);
  611. erroraddress = ((512 + 7) - erroraddress);
  612. errorvalue =
  613. ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
  614. (16 * (i & 1))) & 0xFF);
  615. } else {
  616. erroraddress =
  617. ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
  618. (16 * (i & 1))) & 0x3FF);
  619. erroraddress = ((512 + 7) - erroraddress);
  620. errorvalue =
  621. ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
  622. (16 * (i & 1))) & 0xFF);
  623. }
  624. /* xor the corrupt data with error value */
  625. if (erroraddress < 512)
  626. dat[erroraddress] ^= errorvalue;
  627. }
  628. return numerrors;
  629. }
  630. #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
  631. static int nand_davinci_dev_ready(struct mtd_info *mtd)
  632. {
  633. return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
  634. }
  635. static void davinci_nand_init(struct nand_chip *nand)
  636. {
  637. #if defined CONFIG_KEYSTONE_RBL_NAND
  638. int i;
  639. struct nand_ecclayout *layout;
  640. layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  641. layout->oobavail = 0;
  642. for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
  643. layout->oobfree[i].length; i++)
  644. layout->oobavail += layout->oobfree[i].length;
  645. nand->write_page = nand_davinci_write_page;
  646. nand->ecc.read_page = nand_davinci_read_page_hwecc;
  647. #endif
  648. nand->chip_delay = 0;
  649. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  650. nand->bbt_options |= NAND_BBT_USE_FLASH;
  651. #endif
  652. #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
  653. nand->options |= NAND_NO_SUBPAGE_WRITE;
  654. #endif
  655. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  656. nand->options |= NAND_BUSWIDTH_16;
  657. #endif
  658. #ifdef CONFIG_SYS_NAND_HW_ECC
  659. nand->ecc.mode = NAND_ECC_HW;
  660. nand->ecc.size = 512;
  661. nand->ecc.bytes = 3;
  662. nand->ecc.strength = 1;
  663. nand->ecc.calculate = nand_davinci_calculate_ecc;
  664. nand->ecc.correct = nand_davinci_correct_data;
  665. nand->ecc.hwctl = nand_davinci_enable_hwecc;
  666. #else
  667. nand->ecc.mode = NAND_ECC_SOFT;
  668. #endif /* CONFIG_SYS_NAND_HW_ECC */
  669. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  670. nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
  671. nand->ecc.size = 512;
  672. nand->ecc.bytes = 10;
  673. nand->ecc.strength = 4;
  674. nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
  675. nand->ecc.correct = nand_davinci_4bit_correct_data;
  676. nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
  677. nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
  678. #endif
  679. /* Set address of hardware control function */
  680. nand->cmd_ctrl = nand_davinci_hwcontrol;
  681. nand->read_buf = nand_davinci_read_buf;
  682. nand->write_buf = nand_davinci_write_buf;
  683. nand->dev_ready = nand_davinci_dev_ready;
  684. }
  685. #ifdef CONFIG_SYS_NAND_SELF_INIT
  686. static int davinci_nand_probe(struct udevice *dev)
  687. {
  688. struct nand_chip *nand = dev_get_priv(dev);
  689. struct mtd_info *mtd = nand_to_mtd(nand);
  690. int ret;
  691. nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
  692. nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
  693. davinci_nand_init(nand);
  694. ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
  695. if (ret)
  696. return ret;
  697. return nand_register(0, mtd);
  698. }
  699. static const struct udevice_id davinci_nand_ids[] = {
  700. { .compatible = "ti,davinci-nand" },
  701. { }
  702. };
  703. U_BOOT_DRIVER(davinci_nand) = {
  704. .name = "davinci-nand",
  705. .id = UCLASS_MTD,
  706. .of_match = davinci_nand_ids,
  707. .probe = davinci_nand_probe,
  708. .priv_auto = sizeof(struct nand_chip),
  709. };
  710. void board_nand_init(void)
  711. {
  712. struct udevice *dev;
  713. int ret;
  714. ret = uclass_get_device_by_driver(UCLASS_MTD,
  715. DM_DRIVER_GET(davinci_nand), &dev);
  716. if (ret && ret != -ENODEV)
  717. pr_err("Failed to initialize %s: %d\n", dev->name, ret);
  718. }
  719. #else
  720. int board_nand_init(struct nand_chip *chip) __attribute__((weak));
  721. int board_nand_init(struct nand_chip *chip)
  722. {
  723. davinci_nand_init(chip);
  724. return 0;
  725. }
  726. #endif /* CONFIG_SYS_NAND_SELF_INIT */