bcm6838_nand.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <asm/io.h>
  4. #include <memalign.h>
  5. #include <nand.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include <linux/ioport.h>
  11. #include <dm.h>
  12. #include "brcmnand.h"
  13. struct bcm6838_nand_soc {
  14. struct brcmnand_soc soc;
  15. void __iomem *base;
  16. };
  17. #define BCM6838_NAND_INT 0x00
  18. #define BCM6838_NAND_STATUS_SHIFT 0
  19. #define BCM6838_NAND_STATUS_MASK (0xfff << BCM6838_NAND_STATUS_SHIFT)
  20. #define BCM6838_NAND_ENABLE_SHIFT 16
  21. #define BCM6838_NAND_ENABLE_MASK (0xffff << BCM6838_NAND_ENABLE_SHIFT)
  22. enum {
  23. BCM6838_NP_READ = BIT(0),
  24. BCM6838_BLOCK_ERASE = BIT(1),
  25. BCM6838_COPY_BACK = BIT(2),
  26. BCM6838_PAGE_PGM = BIT(3),
  27. BCM6838_CTRL_READY = BIT(4),
  28. BCM6838_DEV_RBPIN = BIT(5),
  29. BCM6838_ECC_ERR_UNC = BIT(6),
  30. BCM6838_ECC_ERR_CORR = BIT(7),
  31. };
  32. static bool bcm6838_nand_intc_ack(struct brcmnand_soc *soc)
  33. {
  34. struct bcm6838_nand_soc *priv =
  35. container_of(soc, struct bcm6838_nand_soc, soc);
  36. void __iomem *mmio = priv->base + BCM6838_NAND_INT;
  37. u32 val = brcmnand_readl(mmio);
  38. if (val & (BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT)) {
  39. /* Ack interrupt */
  40. val &= ~BCM6838_NAND_STATUS_MASK;
  41. val |= BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT;
  42. brcmnand_writel(val, mmio);
  43. return true;
  44. }
  45. return false;
  46. }
  47. static void bcm6838_nand_intc_set(struct brcmnand_soc *soc, bool en)
  48. {
  49. struct bcm6838_nand_soc *priv =
  50. container_of(soc, struct bcm6838_nand_soc, soc);
  51. void __iomem *mmio = priv->base + BCM6838_NAND_INT;
  52. u32 val = brcmnand_readl(mmio);
  53. /* Don't ack any interrupts */
  54. val &= ~BCM6838_NAND_STATUS_MASK;
  55. if (en)
  56. val |= BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT;
  57. else
  58. val &= ~(BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT);
  59. brcmnand_writel(val, mmio);
  60. }
  61. static int bcm6838_nand_probe(struct udevice *dev)
  62. {
  63. struct udevice *pdev = dev;
  64. struct bcm6838_nand_soc *priv = dev_get_priv(dev);
  65. struct brcmnand_soc *soc;
  66. struct resource res;
  67. soc = &priv->soc;
  68. dev_read_resource_byname(pdev, "nand-int-base", &res);
  69. priv->base = ioremap(res.start, resource_size(&res));
  70. if (IS_ERR(priv->base))
  71. return PTR_ERR(priv->base);
  72. soc->ctlrdy_ack = bcm6838_nand_intc_ack;
  73. soc->ctlrdy_set_enabled = bcm6838_nand_intc_set;
  74. /* Disable and ack all interrupts */
  75. brcmnand_writel(0, priv->base + BCM6838_NAND_INT);
  76. brcmnand_writel(BCM6838_NAND_STATUS_MASK,
  77. priv->base + BCM6838_NAND_INT);
  78. return brcmnand_probe(pdev, soc);
  79. }
  80. static const struct udevice_id bcm6838_nand_dt_ids[] = {
  81. {
  82. .compatible = "brcm,nand-bcm6838",
  83. },
  84. { /* sentinel */ }
  85. };
  86. U_BOOT_DRIVER(bcm6838_nand) = {
  87. .name = "bcm6838-nand",
  88. .id = UCLASS_MTD,
  89. .of_match = bcm6838_nand_dt_ids,
  90. .probe = bcm6838_nand_probe,
  91. .priv_auto = sizeof(struct bcm6838_nand_soc),
  92. };
  93. void board_nand_init(void)
  94. {
  95. struct udevice *dev;
  96. int ret;
  97. ret = uclass_get_device_by_driver(UCLASS_MTD,
  98. DM_DRIVER_GET(bcm6838_nand), &dev);
  99. if (ret && ret != -ENODEV)
  100. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  101. ret);
  102. }