bcm63158_nand.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <asm/io.h>
  4. #include <memalign.h>
  5. #include <nand.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include <linux/ioport.h>
  11. #include <dm.h>
  12. #include "brcmnand.h"
  13. struct bcm63158_nand_soc {
  14. struct brcmnand_soc soc;
  15. void __iomem *base;
  16. };
  17. #define BCM63158_NAND_INT 0x00
  18. #define BCM63158_NAND_STATUS_SHIFT 0
  19. #define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT)
  20. #define BCM63158_NAND_INT_EN 0x04
  21. #define BCM63158_NAND_ENABLE_SHIFT 0
  22. #define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT)
  23. enum {
  24. BCM63158_NP_READ = BIT(0),
  25. BCM63158_BLOCK_ERASE = BIT(1),
  26. BCM63158_COPY_BACK = BIT(2),
  27. BCM63158_PAGE_PGM = BIT(3),
  28. BCM63158_CTRL_READY = BIT(4),
  29. BCM63158_DEV_RBPIN = BIT(5),
  30. BCM63158_ECC_ERR_UNC = BIT(6),
  31. BCM63158_ECC_ERR_CORR = BIT(7),
  32. };
  33. static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
  34. {
  35. struct bcm63158_nand_soc *priv =
  36. container_of(soc, struct bcm63158_nand_soc, soc);
  37. void __iomem *mmio = priv->base + BCM63158_NAND_INT;
  38. u32 val = brcmnand_readl(mmio);
  39. if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
  40. /* Ack interrupt */
  41. val &= ~BCM63158_NAND_STATUS_MASK;
  42. val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
  43. brcmnand_writel(val, mmio);
  44. return true;
  45. }
  46. return false;
  47. }
  48. static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
  49. {
  50. struct bcm63158_nand_soc *priv =
  51. container_of(soc, struct bcm63158_nand_soc, soc);
  52. void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
  53. u32 val = brcmnand_readl(mmio);
  54. /* Don't ack any interrupts */
  55. val &= ~BCM63158_NAND_STATUS_MASK;
  56. if (en)
  57. val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
  58. else
  59. val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
  60. brcmnand_writel(val, mmio);
  61. }
  62. static int bcm63158_nand_probe(struct udevice *dev)
  63. {
  64. struct udevice *pdev = dev;
  65. struct bcm63158_nand_soc *priv = dev_get_priv(dev);
  66. struct brcmnand_soc *soc;
  67. struct resource res;
  68. soc = &priv->soc;
  69. dev_read_resource_byname(pdev, "nand-int-base", &res);
  70. priv->base = devm_ioremap(dev, res.start, resource_size(&res));
  71. if (IS_ERR(priv->base))
  72. return PTR_ERR(priv->base);
  73. soc->ctlrdy_ack = bcm63158_nand_intc_ack;
  74. soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
  75. /* Disable and ack all interrupts */
  76. brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
  77. brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
  78. return brcmnand_probe(pdev, soc);
  79. }
  80. static const struct udevice_id bcm63158_nand_dt_ids[] = {
  81. {
  82. .compatible = "brcm,nand-bcm63158",
  83. },
  84. { /* sentinel */ }
  85. };
  86. U_BOOT_DRIVER(bcm63158_nand) = {
  87. .name = "bcm63158-nand",
  88. .id = UCLASS_MTD,
  89. .of_match = bcm63158_nand_dt_ids,
  90. .probe = bcm63158_nand_probe,
  91. .priv_auto = sizeof(struct bcm63158_nand_soc),
  92. };
  93. void board_nand_init(void)
  94. {
  95. struct udevice *dev;
  96. int ret;
  97. ret = uclass_get_device_by_driver(UCLASS_MTD,
  98. DM_DRIVER_GET(bcm63158_nand), &dev);
  99. if (ret && ret != -ENODEV)
  100. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  101. ret);
  102. }