fu540-prci.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Copyright (C) 2018 SiFive, Inc.
  6. * Wesley Terpstra
  7. * Paul Walmsley
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * The FU540 PRCI implements clock and reset control for the SiFive
  19. * FU540-C000 chip. This driver assumes that it has sole control
  20. * over all PRCI resources.
  21. *
  22. * This driver is based on the PRCI driver written by Wesley Terpstra.
  23. *
  24. * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
  25. * https://github.com/riscv/riscv-linux
  26. *
  27. * References:
  28. * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  29. */
  30. #include <common.h>
  31. #include <clk-uclass.h>
  32. #include <clk.h>
  33. #include <div64.h>
  34. #include <dm.h>
  35. #include <dm/device.h>
  36. #include <dm/device_compat.h>
  37. #include <dm/uclass.h>
  38. #include <dt-bindings/clock/sifive-fu540-prci.h>
  39. #include <dt-bindings/reset/sifive-fu540-prci.h>
  40. #include <errno.h>
  41. #include <reset-uclass.h>
  42. #include <asm/io.h>
  43. #include <asm/arch/reset.h>
  44. #include <linux/delay.h>
  45. #include <linux/err.h>
  46. #include <linux/math64.h>
  47. #include <linux/clk/analogbits-wrpll-cln28hpc.h>
  48. /*
  49. * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  50. * hfclk and rtcclk
  51. */
  52. #define EXPECTED_CLK_PARENT_COUNT 2
  53. /*
  54. * Register offsets and bitmasks
  55. */
  56. /* COREPLLCFG0 */
  57. #define PRCI_COREPLLCFG0_OFFSET 0x4
  58. #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
  59. #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
  60. #define PRCI_COREPLLCFG0_DIVF_SHIFT 6
  61. #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
  62. #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
  63. #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
  64. #define PRCI_COREPLLCFG0_RANGE_SHIFT 18
  65. #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
  66. #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
  67. #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
  68. #define PRCI_COREPLLCFG0_FSE_SHIFT 25
  69. #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
  70. #define PRCI_COREPLLCFG0_LOCK_SHIFT 31
  71. #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
  72. /* COREPLLCFG1 */
  73. #define PRCI_COREPLLCFG1_OFFSET 0x8
  74. #define PRCI_COREPLLCFG1_CKE_SHIFT 31
  75. #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
  76. /* DDRPLLCFG0 */
  77. #define PRCI_DDRPLLCFG0_OFFSET 0xc
  78. #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
  79. #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
  80. #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
  81. #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
  82. #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
  83. #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
  84. #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
  85. #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
  86. #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
  87. #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
  88. #define PRCI_DDRPLLCFG0_FSE_SHIFT 25
  89. #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
  90. #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
  91. #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
  92. /* DDRPLLCFG1 */
  93. #define PRCI_DDRPLLCFG1_OFFSET 0x10
  94. #define PRCI_DDRPLLCFG1_CKE_SHIFT 31
  95. #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
  96. /* GEMGXLPLLCFG0 */
  97. #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
  98. #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
  99. #define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
  100. (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
  101. #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
  102. #define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
  103. (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
  104. #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
  105. #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
  106. #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
  107. #define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
  108. (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
  109. #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
  110. #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
  111. (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
  112. #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
  113. #define PRCI_GEMGXLPLLCFG0_FSE_MASK \
  114. (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
  115. #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
  116. #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
  117. /* GEMGXLPLLCFG1 */
  118. #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
  119. #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
  120. #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
  121. /* CORECLKSEL */
  122. #define PRCI_CORECLKSEL_OFFSET 0x24
  123. #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
  124. #define PRCI_CORECLKSEL_CORECLKSEL_MASK \
  125. (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
  126. /* DEVICESRESETREG */
  127. #define PRCI_DEVICESRESETREG_OFFSET 0x28
  128. #define PRCI_DEVICERESETCNT 5
  129. #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
  130. (0x1 << PRCI_RST_DDR_CTRL_N)
  131. #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
  132. (0x1 << PRCI_RST_DDR_AXI_N)
  133. #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
  134. (0x1 << PRCI_RST_DDR_AHB_N)
  135. #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
  136. (0x1 << PRCI_RST_DDR_PHY_N)
  137. #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
  138. (0x1 << PRCI_RST_GEMGXL_N)
  139. /* CLKMUXSTATUSREG */
  140. #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
  141. #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
  142. #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
  143. (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
  144. /* PROCMONCFG */
  145. #define PRCI_PROCMONCFG_OFFSET 0xF0
  146. #define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
  147. #define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
  148. (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
  149. /*
  150. * Private structures
  151. */
  152. /**
  153. * struct __prci_data - per-device-instance data
  154. * @va: base virtual address of the PRCI IP block
  155. * @parent: parent clk instance
  156. *
  157. * PRCI per-device instance data
  158. */
  159. struct __prci_data {
  160. void *va;
  161. struct clk parent_hfclk;
  162. struct clk parent_rtcclk;
  163. };
  164. /**
  165. * struct __prci_wrpll_data - WRPLL configuration and integration data
  166. * @c: WRPLL current configuration record
  167. * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
  168. * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
  169. * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
  170. * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
  171. * @release_reset: fn ptr to code to release clock reset
  172. *
  173. * @enable_bypass and @disable_bypass are used for WRPLL instances
  174. * that contain a separate external glitchless clock mux downstream
  175. * from the PLL. The WRPLL internal bypass mux is not glitchless.
  176. */
  177. struct __prci_wrpll_data {
  178. struct wrpll_cfg c;
  179. void (*enable_bypass)(struct __prci_data *pd);
  180. void (*disable_bypass)(struct __prci_data *pd);
  181. u8 cfg0_offs;
  182. u8 cfg1_offs;
  183. void (*release_reset)(struct __prci_data *pd);
  184. };
  185. struct __prci_clock;
  186. /* struct __prci_clock_ops - clock operations */
  187. struct __prci_clock_ops {
  188. int (*set_rate)(struct __prci_clock *pc,
  189. unsigned long rate,
  190. unsigned long parent_rate);
  191. unsigned long (*round_rate)(struct __prci_clock *pc,
  192. unsigned long rate,
  193. unsigned long *parent_rate);
  194. unsigned long (*recalc_rate)(struct __prci_clock *pc,
  195. unsigned long parent_rate);
  196. int (*enable_clk)(struct __prci_clock *pc, bool enable);
  197. };
  198. /**
  199. * struct __prci_clock - describes a clock device managed by PRCI
  200. * @name: user-readable clock name string - should match the manual
  201. * @parent_name: parent name for this clock
  202. * @ops: struct __prci_clock_ops for control
  203. * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
  204. * @pd: PRCI-specific data associated with this clock (if not NULL)
  205. *
  206. * PRCI clock data. Used by the PRCI driver to register PRCI-provided
  207. * clocks to the Linux clock infrastructure.
  208. */
  209. struct __prci_clock {
  210. const char *name;
  211. const char *parent_name;
  212. const struct __prci_clock_ops *ops;
  213. struct __prci_wrpll_data *pwd;
  214. struct __prci_data *pd;
  215. };
  216. /*
  217. * Private functions
  218. */
  219. /**
  220. * __prci_readl() - read from a PRCI register
  221. * @pd: PRCI context
  222. * @offs: register offset to read from (in bytes, from PRCI base address)
  223. *
  224. * Read the register located at offset @offs from the base virtual
  225. * address of the PRCI register target described by @pd, and return
  226. * the value to the caller.
  227. *
  228. * Context: Any context.
  229. *
  230. * Return: the contents of the register described by @pd and @offs.
  231. */
  232. static u32 __prci_readl(struct __prci_data *pd, u32 offs)
  233. {
  234. return readl(pd->va + offs);
  235. }
  236. static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
  237. {
  238. writel(v, pd->va + offs);
  239. }
  240. /* WRPLL-related private functions */
  241. /**
  242. * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
  243. * @c: ptr to a struct wrpll_cfg record to write config into
  244. * @r: value read from the PRCI PLL configuration register
  245. *
  246. * Given a value @r read from an FU540 PRCI PLL configuration register,
  247. * split it into fields and populate it into the WRPLL configuration record
  248. * pointed to by @c.
  249. *
  250. * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
  251. * have the same register layout.
  252. *
  253. * Context: Any context.
  254. */
  255. static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
  256. {
  257. u32 v;
  258. v = r & PRCI_COREPLLCFG0_DIVR_MASK;
  259. v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
  260. c->divr = v;
  261. v = r & PRCI_COREPLLCFG0_DIVF_MASK;
  262. v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
  263. c->divf = v;
  264. v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
  265. v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
  266. c->divq = v;
  267. v = r & PRCI_COREPLLCFG0_RANGE_MASK;
  268. v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
  269. c->range = v;
  270. c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
  271. WRPLL_FLAGS_EXT_FEEDBACK_MASK);
  272. /* external feedback mode not supported */
  273. c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
  274. }
  275. /**
  276. * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
  277. * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
  278. *
  279. * Using a set of WRPLL configuration values pointed to by @c,
  280. * assemble a PRCI PLL configuration register value, and return it to
  281. * the caller.
  282. *
  283. * Context: Any context. Caller must ensure that the contents of the
  284. * record pointed to by @c do not change during the execution
  285. * of this function.
  286. *
  287. * Returns: a value suitable for writing into a PRCI PLL configuration
  288. * register
  289. */
  290. static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
  291. {
  292. u32 r = 0;
  293. r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
  294. r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
  295. r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
  296. r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
  297. /* external feedback mode not supported */
  298. r |= PRCI_COREPLLCFG0_FSE_MASK;
  299. return r;
  300. }
  301. /**
  302. * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
  303. * @pd: PRCI context
  304. * @pwd: PRCI WRPLL metadata
  305. *
  306. * Read the current configuration of the PLL identified by @pwd from
  307. * the PRCI identified by @pd, and store it into the local configuration
  308. * cache in @pwd.
  309. *
  310. * Context: Any context. Caller must prevent the records pointed to by
  311. * @pd and @pwd from changing during execution.
  312. */
  313. static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
  314. struct __prci_wrpll_data *pwd)
  315. {
  316. __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
  317. }
  318. /**
  319. * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
  320. * @pd: PRCI context
  321. * @pwd: PRCI WRPLL metadata
  322. * @c: WRPLL configuration record to write
  323. *
  324. * Write the WRPLL configuration described by @c into the WRPLL
  325. * configuration register identified by @pwd in the PRCI instance
  326. * described by @c. Make a cached copy of the WRPLL's current
  327. * configuration so it can be used by other code.
  328. *
  329. * Context: Any context. Caller must prevent the records pointed to by
  330. * @pd and @pwd from changing during execution.
  331. */
  332. static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
  333. struct __prci_wrpll_data *pwd,
  334. struct wrpll_cfg *c)
  335. {
  336. __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
  337. memcpy(&pwd->c, c, sizeof(*c));
  338. }
  339. /**
  340. * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
  341. * into the PRCI
  342. * @pd: PRCI context
  343. * @pwd: PRCI WRPLL metadata
  344. * @enable: Clock enable or disable value
  345. */
  346. static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
  347. struct __prci_wrpll_data *pwd,
  348. u32 enable)
  349. {
  350. __prci_writel(enable, pwd->cfg1_offs, pd);
  351. }
  352. /* Core clock mux control */
  353. /**
  354. * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
  355. * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
  356. *
  357. * Switch the CORECLK mux to the HFCLK input source; return once complete.
  358. *
  359. * Context: Any context. Caller must prevent concurrent changes to the
  360. * PRCI_CORECLKSEL_OFFSET register.
  361. */
  362. static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
  363. {
  364. u32 r;
  365. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
  366. r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
  367. __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
  368. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
  369. }
  370. /**
  371. * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
  372. * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
  373. *
  374. * Switch the CORECLK mux to the PLL output clock; return once complete.
  375. *
  376. * Context: Any context. Caller must prevent concurrent changes to the
  377. * PRCI_CORECLKSEL_OFFSET register.
  378. */
  379. static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
  380. {
  381. u32 r;
  382. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
  383. r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
  384. __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
  385. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
  386. }
  387. static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
  388. struct __prci_clock *pc,
  389. unsigned long parent_rate)
  390. {
  391. struct __prci_wrpll_data *pwd = pc->pwd;
  392. return wrpll_calc_output_rate(&pwd->c, parent_rate);
  393. }
  394. static unsigned long sifive_fu540_prci_wrpll_round_rate(
  395. struct __prci_clock *pc,
  396. unsigned long rate,
  397. unsigned long *parent_rate)
  398. {
  399. struct __prci_wrpll_data *pwd = pc->pwd;
  400. struct wrpll_cfg c;
  401. memcpy(&c, &pwd->c, sizeof(c));
  402. wrpll_configure_for_rate(&c, rate, *parent_rate);
  403. return wrpll_calc_output_rate(&c, *parent_rate);
  404. }
  405. static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
  406. unsigned long rate,
  407. unsigned long parent_rate)
  408. {
  409. struct __prci_wrpll_data *pwd = pc->pwd;
  410. struct __prci_data *pd = pc->pd;
  411. int r;
  412. r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
  413. if (r)
  414. return r;
  415. if (pwd->enable_bypass)
  416. pwd->enable_bypass(pd);
  417. __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
  418. udelay(wrpll_calc_max_lock_us(&pwd->c));
  419. if (pwd->disable_bypass)
  420. pwd->disable_bypass(pd);
  421. return 0;
  422. }
  423. static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
  424. {
  425. struct __prci_wrpll_data *pwd = pc->pwd;
  426. struct __prci_data *pd = pc->pd;
  427. if (enable) {
  428. __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
  429. if (pwd->release_reset)
  430. pwd->release_reset(pd);
  431. } else {
  432. u32 r;
  433. r = __prci_readl(pd, pwd->cfg1_offs);
  434. r &= ~PRCI_COREPLLCFG1_CKE_MASK;
  435. __prci_wrpll_write_cfg1(pd, pwd, r);
  436. }
  437. return 0;
  438. }
  439. static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
  440. .set_rate = sifive_fu540_prci_wrpll_set_rate,
  441. .round_rate = sifive_fu540_prci_wrpll_round_rate,
  442. .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
  443. .enable_clk = sifive_fu540_prci_clock_enable,
  444. };
  445. /* TLCLKSEL clock integration */
  446. static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
  447. struct __prci_clock *pc,
  448. unsigned long parent_rate)
  449. {
  450. struct __prci_data *pd = pc->pd;
  451. u32 v;
  452. u8 div;
  453. v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
  454. v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
  455. div = v ? 1 : 2;
  456. return div_u64(parent_rate, div);
  457. }
  458. static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
  459. .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
  460. };
  461. static int __prci_consumer_reset(const char *rst_name, bool trigger)
  462. {
  463. struct udevice *dev;
  464. struct reset_ctl rst_sig;
  465. int ret;
  466. ret = uclass_get_device_by_driver(UCLASS_RESET,
  467. DM_DRIVER_GET(sifive_reset),
  468. &dev);
  469. if (ret) {
  470. dev_err(dev, "Reset driver not found: %d\n", ret);
  471. return ret;
  472. }
  473. ret = reset_get_by_name(dev, rst_name, &rst_sig);
  474. if (ret) {
  475. dev_err(dev, "failed to get %s reset\n", rst_name);
  476. return ret;
  477. }
  478. if (reset_valid(&rst_sig)) {
  479. if (trigger)
  480. ret = reset_deassert(&rst_sig);
  481. else
  482. ret = reset_assert(&rst_sig);
  483. if (ret) {
  484. dev_err(dev, "failed to trigger reset id = %ld\n",
  485. rst_sig.id);
  486. return ret;
  487. }
  488. }
  489. return ret;
  490. }
  491. /**
  492. * __prci_ddr_release_reset() - Release DDR reset
  493. * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
  494. *
  495. */
  496. static void __prci_ddr_release_reset(struct __prci_data *pd)
  497. {
  498. /* Release DDR ctrl reset */
  499. __prci_consumer_reset("ddr_ctrl", true);
  500. /* HACK to get the '1 full controller clock cycle'. */
  501. asm volatile ("fence");
  502. /* Release DDR AXI reset */
  503. __prci_consumer_reset("ddr_axi", true);
  504. /* Release DDR AHB reset */
  505. __prci_consumer_reset("ddr_ahb", true);
  506. /* Release DDR PHY reset */
  507. __prci_consumer_reset("ddr_phy", true);
  508. /* HACK to get the '1 full controller clock cycle'. */
  509. asm volatile ("fence");
  510. /*
  511. * These take like 16 cycles to actually propagate. We can't go sending
  512. * stuff before they come out of reset. So wait.
  513. */
  514. for (int i = 0; i < 256; i++)
  515. asm volatile ("nop");
  516. }
  517. /**
  518. * __prci_ethernet_release_reset() - Release ethernet reset
  519. * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
  520. *
  521. */
  522. static void __prci_ethernet_release_reset(struct __prci_data *pd)
  523. {
  524. /* Release GEMGXL reset */
  525. __prci_consumer_reset("gemgxl_reset", true);
  526. /* Procmon => core clock */
  527. __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
  528. pd);
  529. }
  530. /*
  531. * PRCI integration data for each WRPLL instance
  532. */
  533. static struct __prci_wrpll_data __prci_corepll_data = {
  534. .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
  535. .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
  536. .enable_bypass = __prci_coreclksel_use_hfclk,
  537. .disable_bypass = __prci_coreclksel_use_corepll,
  538. };
  539. static struct __prci_wrpll_data __prci_ddrpll_data = {
  540. .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
  541. .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
  542. .release_reset = __prci_ddr_release_reset,
  543. };
  544. static struct __prci_wrpll_data __prci_gemgxlpll_data = {
  545. .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
  546. .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
  547. .release_reset = __prci_ethernet_release_reset,
  548. };
  549. /*
  550. * List of clock controls provided by the PRCI
  551. */
  552. static struct __prci_clock __prci_init_clocks[] = {
  553. [PRCI_CLK_COREPLL] = {
  554. .name = "corepll",
  555. .parent_name = "hfclk",
  556. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  557. .pwd = &__prci_corepll_data,
  558. },
  559. [PRCI_CLK_DDRPLL] = {
  560. .name = "ddrpll",
  561. .parent_name = "hfclk",
  562. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  563. .pwd = &__prci_ddrpll_data,
  564. },
  565. [PRCI_CLK_GEMGXLPLL] = {
  566. .name = "gemgxlpll",
  567. .parent_name = "hfclk",
  568. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  569. .pwd = &__prci_gemgxlpll_data,
  570. },
  571. [PRCI_CLK_TLCLK] = {
  572. .name = "tlclk",
  573. .parent_name = "corepll",
  574. .ops = &sifive_fu540_prci_tlclksel_clk_ops,
  575. },
  576. };
  577. static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
  578. {
  579. ulong parent_rate;
  580. struct __prci_clock *p;
  581. if (strcmp(pc->parent_name, "corepll") == 0) {
  582. p = &__prci_init_clocks[PRCI_CLK_COREPLL];
  583. if (!p->pd || !p->ops->recalc_rate)
  584. return -ENXIO;
  585. return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
  586. }
  587. if (strcmp(pc->parent_name, "rtcclk") == 0)
  588. parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
  589. else
  590. parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
  591. return parent_rate;
  592. }
  593. static ulong sifive_fu540_prci_get_rate(struct clk *clk)
  594. {
  595. struct __prci_clock *pc;
  596. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  597. return -ENXIO;
  598. pc = &__prci_init_clocks[clk->id];
  599. if (!pc->pd || !pc->ops->recalc_rate)
  600. return -ENXIO;
  601. return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
  602. }
  603. static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
  604. {
  605. int err;
  606. struct __prci_clock *pc;
  607. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  608. return -ENXIO;
  609. pc = &__prci_init_clocks[clk->id];
  610. if (!pc->pd || !pc->ops->set_rate)
  611. return -ENXIO;
  612. err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
  613. if (err)
  614. return err;
  615. return rate;
  616. }
  617. static int sifive_fu540_prci_enable(struct clk *clk)
  618. {
  619. struct __prci_clock *pc;
  620. int ret = 0;
  621. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  622. return -ENXIO;
  623. pc = &__prci_init_clocks[clk->id];
  624. if (!pc->pd)
  625. return -ENXIO;
  626. if (pc->ops->enable_clk)
  627. ret = pc->ops->enable_clk(pc, 1);
  628. return ret;
  629. }
  630. static int sifive_fu540_prci_disable(struct clk *clk)
  631. {
  632. struct __prci_clock *pc;
  633. int ret = 0;
  634. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  635. return -ENXIO;
  636. pc = &__prci_init_clocks[clk->id];
  637. if (!pc->pd)
  638. return -ENXIO;
  639. if (pc->ops->enable_clk)
  640. ret = pc->ops->enable_clk(pc, 0);
  641. return ret;
  642. }
  643. static int sifive_fu540_prci_probe(struct udevice *dev)
  644. {
  645. int i, err;
  646. struct __prci_clock *pc;
  647. struct __prci_data *pd = dev_get_priv(dev);
  648. pd->va = (void *)dev_read_addr(dev);
  649. if (IS_ERR(pd->va))
  650. return PTR_ERR(pd->va);
  651. err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
  652. if (err)
  653. return err;
  654. err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
  655. if (err)
  656. return err;
  657. for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
  658. pc = &__prci_init_clocks[i];
  659. pc->pd = pd;
  660. if (pc->pwd)
  661. __prci_wrpll_read_cfg0(pd, pc->pwd);
  662. }
  663. return 0;
  664. }
  665. static struct clk_ops sifive_fu540_prci_ops = {
  666. .set_rate = sifive_fu540_prci_set_rate,
  667. .get_rate = sifive_fu540_prci_get_rate,
  668. .enable = sifive_fu540_prci_enable,
  669. .disable = sifive_fu540_prci_disable,
  670. };
  671. static int sifive_fu540_clk_bind(struct udevice *dev)
  672. {
  673. return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
  674. }
  675. static const struct udevice_id sifive_fu540_prci_ids[] = {
  676. { .compatible = "sifive,fu540-c000-prci" },
  677. { }
  678. };
  679. U_BOOT_DRIVER(sifive_fu540_prci) = {
  680. .name = "sifive-fu540-prci",
  681. .id = UCLASS_CLK,
  682. .of_match = sifive_fu540_prci_ids,
  683. .probe = sifive_fu540_prci_probe,
  684. .ops = &sifive_fu540_prci_ops,
  685. .priv_auto = sizeof(struct __prci_data),
  686. .bind = sifive_fu540_clk_bind,
  687. };