board.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741
  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <adc.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <asm/arch/stm32.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/gpio.h>
  12. #include <asm/io.h>
  13. #include <bootm.h>
  14. #include <clk.h>
  15. #include <config.h>
  16. #include <dm.h>
  17. #include <dm/device.h>
  18. #include <dm/uclass.h>
  19. #include <env.h>
  20. #include <env_internal.h>
  21. #include <g_dnl.h>
  22. #include <generic-phy.h>
  23. #include <hang.h>
  24. #include <i2c.h>
  25. #include <i2c_eeprom.h>
  26. #include <init.h>
  27. #include <led.h>
  28. #include <memalign.h>
  29. #include <misc.h>
  30. #include <mtd.h>
  31. #include <mtd_node.h>
  32. #include <netdev.h>
  33. #include <phy.h>
  34. #include <linux/bitops.h>
  35. #include <linux/delay.h>
  36. #include <power/regulator.h>
  37. #include <remoteproc.h>
  38. #include <reset.h>
  39. #include <syscon.h>
  40. #include <usb.h>
  41. #include <usb/dwc2_udc.h>
  42. #include <watchdog.h>
  43. #include "../../st/common/stpmic1.h"
  44. /* SYSCFG registers */
  45. #define SYSCFG_BOOTR 0x00
  46. #define SYSCFG_PMCSETR 0x04
  47. #define SYSCFG_IOCTRLSETR 0x18
  48. #define SYSCFG_ICNR 0x1C
  49. #define SYSCFG_CMPCR 0x20
  50. #define SYSCFG_CMPENSETR 0x24
  51. #define SYSCFG_PMCCLRR 0x44
  52. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  53. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  54. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  55. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  56. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  57. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  58. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  59. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  60. #define SYSCFG_CMPCR_READY BIT(8)
  61. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  62. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  63. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  64. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  65. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  66. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  67. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  68. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  69. /*
  70. * Get a global data pointer
  71. */
  72. DECLARE_GLOBAL_DATA_PTR;
  73. #define KS_CCR 0x08
  74. #define KS_CCR_EEPROM BIT(9)
  75. #define KS_BE0 BIT(12)
  76. #define KS_BE1 BIT(13)
  77. int setup_mac_address(void)
  78. {
  79. unsigned char enetaddr[6];
  80. bool skip_eth0 = false;
  81. bool skip_eth1 = false;
  82. struct udevice *dev;
  83. int off, ret;
  84. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  85. if (ret) /* ethaddr is already set */
  86. skip_eth0 = true;
  87. off = fdt_path_offset(gd->fdt_blob, "ethernet1");
  88. if (off < 0) {
  89. /* ethernet1 is not present in the system */
  90. skip_eth1 = true;
  91. goto out_set_ethaddr;
  92. }
  93. ret = eth_env_get_enetaddr("eth1addr", enetaddr);
  94. if (ret) {
  95. /* eth1addr is already set */
  96. skip_eth1 = true;
  97. goto out_set_ethaddr;
  98. }
  99. ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
  100. if (ret)
  101. goto out_set_ethaddr;
  102. /*
  103. * KS8851 with EEPROM may use custom MAC from EEPROM, read
  104. * out the KS8851 CCR register to determine whether EEPROM
  105. * is present. If EEPROM is present, it must contain valid
  106. * MAC address.
  107. */
  108. u32 reg, ccr;
  109. reg = fdt_get_base_address(gd->fdt_blob, off);
  110. if (!reg)
  111. goto out_set_ethaddr;
  112. writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
  113. ccr = readw(reg);
  114. if (ccr & KS_CCR_EEPROM) {
  115. skip_eth1 = true;
  116. goto out_set_ethaddr;
  117. }
  118. out_set_ethaddr:
  119. if (skip_eth0 && skip_eth1)
  120. return 0;
  121. off = fdt_path_offset(gd->fdt_blob, "eeprom0");
  122. if (off < 0) {
  123. printf("%s: No eeprom0 path offset\n", __func__);
  124. return off;
  125. }
  126. ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
  127. if (ret) {
  128. printf("Cannot find EEPROM!\n");
  129. return ret;
  130. }
  131. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  132. if (ret) {
  133. printf("Error reading configuration EEPROM!\n");
  134. return ret;
  135. }
  136. if (is_valid_ethaddr(enetaddr)) {
  137. if (!skip_eth0)
  138. eth_env_set_enetaddr("ethaddr", enetaddr);
  139. enetaddr[5]++;
  140. if (!skip_eth1)
  141. eth_env_set_enetaddr("eth1addr", enetaddr);
  142. }
  143. return 0;
  144. }
  145. int checkboard(void)
  146. {
  147. char *mode;
  148. const char *fdt_compat;
  149. int fdt_compat_len;
  150. if (IS_ENABLED(CONFIG_TFABOOT))
  151. mode = "trusted";
  152. else
  153. mode = "basic";
  154. printf("Board: stm32mp1 in %s mode", mode);
  155. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  156. &fdt_compat_len);
  157. if (fdt_compat && fdt_compat_len)
  158. printf(" (%s)", fdt_compat);
  159. puts("\n");
  160. return 0;
  161. }
  162. #ifdef CONFIG_BOARD_EARLY_INIT_F
  163. static u8 brdcode __section("data");
  164. static u8 ddr3code __section("data");
  165. static u8 somcode __section("data");
  166. static u32 opp_voltage_mv __section(".data");
  167. static void board_get_coding_straps(void)
  168. {
  169. struct gpio_desc gpio[4];
  170. ofnode node;
  171. int i, ret;
  172. node = ofnode_path("/config");
  173. if (!ofnode_valid(node)) {
  174. printf("%s: no /config node?\n", __func__);
  175. return;
  176. }
  177. brdcode = 0;
  178. ddr3code = 0;
  179. somcode = 0;
  180. ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
  181. gpio, ARRAY_SIZE(gpio),
  182. GPIOD_IS_IN);
  183. for (i = 0; i < ret; i++)
  184. somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  185. ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
  186. gpio, ARRAY_SIZE(gpio),
  187. GPIOD_IS_IN);
  188. for (i = 0; i < ret; i++)
  189. ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
  190. ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
  191. gpio, ARRAY_SIZE(gpio),
  192. GPIOD_IS_IN);
  193. for (i = 0; i < ret; i++)
  194. brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  195. printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
  196. somcode, ddr3code, brdcode);
  197. }
  198. int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  199. const char *name)
  200. {
  201. if (ddr3code == 1 &&
  202. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
  203. return 0;
  204. if (ddr3code == 2 &&
  205. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
  206. return 0;
  207. if (ddr3code == 3 &&
  208. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
  209. return 0;
  210. return -EINVAL;
  211. }
  212. void board_vddcore_init(u32 voltage_mv)
  213. {
  214. if (IS_ENABLED(CONFIG_SPL_BUILD))
  215. opp_voltage_mv = voltage_mv;
  216. }
  217. int board_early_init_f(void)
  218. {
  219. if (IS_ENABLED(CONFIG_SPL_BUILD))
  220. stpmic1_init(opp_voltage_mv);
  221. board_get_coding_straps();
  222. return 0;
  223. }
  224. #ifdef CONFIG_SPL_LOAD_FIT
  225. int board_fit_config_name_match(const char *name)
  226. {
  227. const char *compat;
  228. char test[128];
  229. compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
  230. snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
  231. compat, somcode, brdcode);
  232. if (!strcmp(name, test))
  233. return 0;
  234. return -EINVAL;
  235. }
  236. #endif
  237. #endif
  238. static void board_key_check(void)
  239. {
  240. #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
  241. ofnode node;
  242. struct gpio_desc gpio;
  243. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  244. node = ofnode_path("/config");
  245. if (!ofnode_valid(node)) {
  246. debug("%s: no /config node?\n", __func__);
  247. return;
  248. }
  249. #ifdef CONFIG_FASTBOOT
  250. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  251. &gpio, GPIOD_IS_IN)) {
  252. debug("%s: could not find a /config/st,fastboot-gpios\n",
  253. __func__);
  254. } else {
  255. if (dm_gpio_get_value(&gpio)) {
  256. puts("Fastboot key pressed, ");
  257. boot_mode = BOOT_FASTBOOT;
  258. }
  259. dm_gpio_free(NULL, &gpio);
  260. }
  261. #endif
  262. #ifdef CONFIG_CMD_STM32PROG
  263. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  264. &gpio, GPIOD_IS_IN)) {
  265. debug("%s: could not find a /config/st,stm32prog-gpios\n",
  266. __func__);
  267. } else {
  268. if (dm_gpio_get_value(&gpio)) {
  269. puts("STM32Programmer key pressed, ");
  270. boot_mode = BOOT_STM32PROG;
  271. }
  272. dm_gpio_free(NULL, &gpio);
  273. }
  274. #endif
  275. if (boot_mode != BOOT_NORMAL) {
  276. puts("entering download mode...\n");
  277. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  278. TAMP_BOOT_FORCED_MASK,
  279. boot_mode);
  280. }
  281. #endif
  282. }
  283. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  284. #include <usb/dwc2_udc.h>
  285. int g_dnl_board_usb_cable_connected(void)
  286. {
  287. struct udevice *dwc2_udc_otg;
  288. int ret;
  289. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  290. DM_DRIVER_GET(dwc2_udc_otg),
  291. &dwc2_udc_otg);
  292. if (!ret)
  293. debug("dwc2_udc_otg init failed\n");
  294. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  295. }
  296. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  297. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  298. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  299. {
  300. if (!strcmp(name, "usb_dnl_dfu"))
  301. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  302. else if (!strcmp(name, "usb_dnl_fastboot"))
  303. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  304. &dev->idProduct);
  305. else
  306. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  307. return 0;
  308. }
  309. #endif /* CONFIG_USB_GADGET */
  310. #ifdef CONFIG_LED
  311. static int get_led(struct udevice **dev, char *led_string)
  312. {
  313. char *led_name;
  314. int ret;
  315. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  316. if (!led_name) {
  317. pr_debug("%s: could not find %s config string\n",
  318. __func__, led_string);
  319. return -ENOENT;
  320. }
  321. ret = led_get_by_label(led_name, dev);
  322. if (ret) {
  323. debug("%s: get=%d\n", __func__, ret);
  324. return ret;
  325. }
  326. return 0;
  327. }
  328. static int setup_led(enum led_state_t cmd)
  329. {
  330. struct udevice *dev;
  331. int ret;
  332. ret = get_led(&dev, "u-boot,boot-led");
  333. if (ret)
  334. return ret;
  335. ret = led_set_state(dev, cmd);
  336. return ret;
  337. }
  338. #endif
  339. static void __maybe_unused led_error_blink(u32 nb_blink)
  340. {
  341. #ifdef CONFIG_LED
  342. int ret;
  343. struct udevice *led;
  344. u32 i;
  345. #endif
  346. if (!nb_blink)
  347. return;
  348. #ifdef CONFIG_LED
  349. ret = get_led(&led, "u-boot,error-led");
  350. if (!ret) {
  351. /* make u-boot,error-led blinking */
  352. /* if U32_MAX and 125ms interval, for 17.02 years */
  353. for (i = 0; i < 2 * nb_blink; i++) {
  354. led_set_state(led, LEDST_TOGGLE);
  355. mdelay(125);
  356. WATCHDOG_RESET();
  357. }
  358. }
  359. #endif
  360. /* infinite: the boot process must be stopped */
  361. if (nb_blink == U32_MAX)
  362. hang();
  363. }
  364. static void sysconf_init(void)
  365. {
  366. #ifndef CONFIG_TFABOOT
  367. u8 *syscfg;
  368. #ifdef CONFIG_DM_REGULATOR
  369. struct udevice *pwr_dev;
  370. struct udevice *pwr_reg;
  371. struct udevice *dev;
  372. int ret;
  373. u32 otp = 0;
  374. #endif
  375. u32 bootr;
  376. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  377. /* interconnect update : select master using the port 1 */
  378. /* LTDC = AXI_M9 */
  379. /* GPU = AXI_M8 */
  380. /* today information is hardcoded in U-Boot */
  381. writel(BIT(9), syscfg + SYSCFG_ICNR);
  382. /* disable Pull-Down for boot pin connected to VDD */
  383. bootr = readl(syscfg + SYSCFG_BOOTR);
  384. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  385. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  386. writel(bootr, syscfg + SYSCFG_BOOTR);
  387. #ifdef CONFIG_DM_REGULATOR
  388. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  389. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  390. * The customer will have to disable this for low frequencies
  391. * or if AFMUX is selected but the function not used, typically for
  392. * TRACE. Otherwise, impact on power consumption.
  393. *
  394. * WARNING:
  395. * enabling High Speed mode while VDD>2.7V
  396. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  397. * erroneously set to 1 can damage the IC!
  398. * => U-Boot set the register only if VDD < 2.7V (in DT)
  399. * but this value need to be consistent with board design
  400. */
  401. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  402. DM_DRIVER_GET(stm32mp_pwr_pmic),
  403. &pwr_dev);
  404. if (!ret) {
  405. ret = uclass_get_device_by_driver(UCLASS_MISC,
  406. DM_DRIVER_GET(stm32mp_bsec),
  407. &dev);
  408. if (ret) {
  409. pr_err("Can't find stm32mp_bsec driver\n");
  410. return;
  411. }
  412. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  413. if (ret > 0)
  414. otp = otp & BIT(13);
  415. /* get VDD = vdd-supply */
  416. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  417. &pwr_reg);
  418. /* check if VDD is Low Voltage */
  419. if (!ret) {
  420. if (regulator_get_value(pwr_reg) < 2700000) {
  421. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  422. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  423. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  424. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  425. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  426. syscfg + SYSCFG_IOCTRLSETR);
  427. if (!otp)
  428. pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  429. } else {
  430. if (otp)
  431. pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  432. }
  433. } else {
  434. debug("VDD unknown");
  435. }
  436. }
  437. #endif
  438. /* activate automatic I/O compensation
  439. * warning: need to ensure CSI enabled and ready in clock driver
  440. */
  441. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  442. while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
  443. ;
  444. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  445. #endif
  446. }
  447. static void board_init_fmc2(void)
  448. {
  449. #define STM32_FMC2_BCR1 0x0
  450. #define STM32_FMC2_BTR1 0x4
  451. #define STM32_FMC2_BWTR1 0x104
  452. #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
  453. #define STM32_FMC2_BCRx_FMCEN BIT(31)
  454. #define STM32_FMC2_BCRx_WREN BIT(12)
  455. #define STM32_FMC2_BCRx_RSVD BIT(7)
  456. #define STM32_FMC2_BCRx_FACCEN BIT(6)
  457. #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
  458. #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
  459. #define STM32_FMC2_BCRx_MUXEN BIT(1)
  460. #define STM32_FMC2_BCRx_MBKEN BIT(0)
  461. #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
  462. #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
  463. #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
  464. #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
  465. #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
  466. #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
  467. #define RCC_MP_AHB6RSTCLRR 0x218
  468. #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
  469. #define RCC_MP_AHB6ENSETR 0x19c
  470. #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
  471. const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
  472. STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
  473. STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
  474. STM32_FMC2_BCRx_MBKEN;
  475. const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
  476. STM32_FMC2_BTRx_BUSTURN(2) |
  477. STM32_FMC2_BTRx_DATAST(0x22) |
  478. STM32_FMC2_BTRx_ADDHLD(2) |
  479. STM32_FMC2_BTRx_ADDSET(2);
  480. /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
  481. writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
  482. writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
  483. /* KS8851-16MLL -- Muxed mode */
  484. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
  485. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
  486. /* AS7C34098 SRAM on X11 -- Muxed mode */
  487. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
  488. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
  489. setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
  490. }
  491. /* board dependent setup after realloc */
  492. int board_init(void)
  493. {
  494. /* address of boot parameters */
  495. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  496. if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
  497. gpio_hog_probe_all();
  498. board_key_check();
  499. #ifdef CONFIG_DM_REGULATOR
  500. regulators_enable_boot_on(_DEBUG);
  501. #endif
  502. sysconf_init();
  503. board_init_fmc2();
  504. if (CONFIG_IS_ENABLED(LED))
  505. led_default_state();
  506. return 0;
  507. }
  508. int board_late_init(void)
  509. {
  510. char *boot_device;
  511. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  512. const void *fdt_compat;
  513. int fdt_compat_len;
  514. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  515. &fdt_compat_len);
  516. if (fdt_compat && fdt_compat_len) {
  517. if (strncmp(fdt_compat, "st,", 3) != 0)
  518. env_set("board_name", fdt_compat);
  519. else
  520. env_set("board_name", fdt_compat + 3);
  521. }
  522. #endif
  523. /* Check the boot-source to disable bootdelay */
  524. boot_device = env_get("boot_device");
  525. if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
  526. env_set("bootdelay", "0");
  527. #ifdef CONFIG_BOARD_EARLY_INIT_F
  528. env_set_ulong("dh_som_rev", somcode);
  529. env_set_ulong("dh_board_rev", brdcode);
  530. env_set_ulong("dh_ddr3_code", ddr3code);
  531. #endif
  532. return 0;
  533. }
  534. void board_quiesce_devices(void)
  535. {
  536. #ifdef CONFIG_LED
  537. setup_led(LEDST_OFF);
  538. #endif
  539. }
  540. /* eth init function : weak called in eqos driver */
  541. int board_interface_eth_init(struct udevice *dev,
  542. phy_interface_t interface_type)
  543. {
  544. u8 *syscfg;
  545. u32 value;
  546. bool eth_clk_sel_reg = false;
  547. bool eth_ref_clk_sel_reg = false;
  548. /* Gigabit Ethernet 125MHz clock selection. */
  549. eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  550. /* Ethernet 50Mhz RMII clock selection */
  551. eth_ref_clk_sel_reg =
  552. dev_read_bool(dev, "st,eth_ref_clk_sel");
  553. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  554. if (!syscfg)
  555. return -ENODEV;
  556. switch (interface_type) {
  557. case PHY_INTERFACE_MODE_MII:
  558. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  559. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  560. debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  561. break;
  562. case PHY_INTERFACE_MODE_GMII:
  563. if (eth_clk_sel_reg)
  564. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  565. SYSCFG_PMCSETR_ETH_CLK_SEL;
  566. else
  567. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  568. debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  569. break;
  570. case PHY_INTERFACE_MODE_RMII:
  571. if (eth_ref_clk_sel_reg)
  572. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  573. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  574. else
  575. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  576. debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  577. break;
  578. case PHY_INTERFACE_MODE_RGMII:
  579. case PHY_INTERFACE_MODE_RGMII_ID:
  580. case PHY_INTERFACE_MODE_RGMII_RXID:
  581. case PHY_INTERFACE_MODE_RGMII_TXID:
  582. if (eth_clk_sel_reg)
  583. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  584. SYSCFG_PMCSETR_ETH_CLK_SEL;
  585. else
  586. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  587. debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  588. break;
  589. default:
  590. debug("%s: Do not manage %d interface\n",
  591. __func__, interface_type);
  592. /* Do not manage others interfaces */
  593. return -EINVAL;
  594. }
  595. /* clear and set ETH configuration bits */
  596. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  597. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  598. syscfg + SYSCFG_PMCCLRR);
  599. writel(value, syscfg + SYSCFG_PMCSETR);
  600. return 0;
  601. }
  602. #if defined(CONFIG_OF_BOARD_SETUP)
  603. int ft_board_setup(void *blob, struct bd_info *bd)
  604. {
  605. return 0;
  606. }
  607. #endif
  608. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  609. {
  610. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  611. if (!rproc_is_initialized())
  612. if (rproc_init()) {
  613. printf("Remote Processor %d initialization failed\n",
  614. id);
  615. return;
  616. }
  617. ret = rproc_load(id, fw_image, fw_size);
  618. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  619. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  620. if (!ret) {
  621. rproc_start(id);
  622. env_set("copro_state", "booted");
  623. }
  624. }
  625. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);