clk.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
  4. * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <asm/arch/clk.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. static const char * const clk_names[clk_max] = {
  14. "armpll", "ddrpll", "iopll",
  15. "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  16. "ddr2x", "ddr3x", "dci",
  17. "lqspi", "smc", "pcap", "gem0", "gem1",
  18. "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  19. "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  20. "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  21. "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  22. "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  23. "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  24. "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  25. };
  26. /**
  27. * set_cpu_clk_info() - Setup clock information
  28. *
  29. * This function is called from common code after relocation and sets up the
  30. * clock information.
  31. */
  32. int set_cpu_clk_info(void)
  33. {
  34. struct clk clk;
  35. struct udevice *dev;
  36. ulong rate;
  37. int i, ret;
  38. ret = uclass_get_device_by_driver(UCLASS_CLK,
  39. DM_DRIVER_GET(zynq_clk), &dev);
  40. if (ret)
  41. return ret;
  42. for (i = 0; i < 2; i++) {
  43. clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  44. ret = clk_request(dev, &clk);
  45. if (ret < 0)
  46. return ret;
  47. rate = clk_get_rate(&clk) / 1000000;
  48. if (i)
  49. gd->bd->bi_ddr_freq = rate;
  50. else
  51. gd->bd->bi_arm_freq = rate;
  52. clk_free(&clk);
  53. }
  54. gd->bd->bi_dsp_freq = 0;
  55. return 0;
  56. }
  57. /**
  58. * soc_clk_dump() - Print clock frequencies
  59. * Returns zero on success
  60. *
  61. * Implementation for the clk dump command.
  62. */
  63. int soc_clk_dump(void)
  64. {
  65. struct udevice *dev;
  66. int i, ret;
  67. ret = uclass_get_device_by_driver(UCLASS_CLK,
  68. DM_DRIVER_GET(zynq_clk), &dev);
  69. if (ret)
  70. return ret;
  71. printf("clk\t\tfrequency\n");
  72. for (i = 0; i < clk_max; i++) {
  73. const char *name = clk_names[i];
  74. if (name) {
  75. struct clk clk;
  76. unsigned long rate;
  77. clk.id = i;
  78. ret = clk_request(dev, &clk);
  79. if (ret < 0)
  80. return ret;
  81. rate = clk_get_rate(&clk);
  82. clk_free(&clk);
  83. if ((rate == (unsigned long)-ENOSYS) ||
  84. (rate == (unsigned long)-ENXIO))
  85. printf("%10s%20s\n", name, "unknown");
  86. else
  87. printf("%10s%20lu\n", name, rate);
  88. }
  89. }
  90. return 0;
  91. }