am6_init.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * AM6: SoC specific initialization
  4. *
  5. * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <fdt_support.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <spl.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sysfw-loader.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include "common.h"
  17. #include <dm.h>
  18. #include <dm/uclass-internal.h>
  19. #include <dm/pinctrl.h>
  20. #include <linux/soc/ti/ti_sci_protocol.h>
  21. #include <log.h>
  22. #include <mmc.h>
  23. #include <stdlib.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_SPL_BUILD
  26. #ifdef CONFIG_K3_LOAD_SYSFW
  27. #ifdef CONFIG_TI_SECURE_DEVICE
  28. struct fwl_data main_cbass_fwls[] = {
  29. { "MMCSD1_CFG", 2057, 1 },
  30. { "MMCSD0_CFG", 2058, 1 },
  31. { "USB3SS0_SLV0", 2176, 2 },
  32. { "PCIE0_SLV", 2336, 8 },
  33. { "PCIE1_SLV", 2337, 8 },
  34. { "PCIE0_CFG", 2688, 1 },
  35. { "PCIE1_CFG", 2689, 1 },
  36. }, mcu_cbass_fwls[] = {
  37. { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  38. { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  39. { "MCU_FSS0_S1", 1033, 8 },
  40. { "MCU_FSS0_S0", 1036, 8 },
  41. { "MCU_CPSW0", 1220, 1 },
  42. };
  43. #endif
  44. #endif
  45. static void ctrl_mmr_unlock(void)
  46. {
  47. /* Unlock all WKUP_CTRL_MMR0 module registers */
  48. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  49. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  50. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  51. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  52. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  53. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  54. /* Unlock all MCU_CTRL_MMR0 module registers */
  55. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  56. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  57. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  58. mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  59. /* Unlock all CTRL_MMR0 module registers */
  60. mmr_unlock(CTRL_MMR0_BASE, 0);
  61. mmr_unlock(CTRL_MMR0_BASE, 1);
  62. mmr_unlock(CTRL_MMR0_BASE, 2);
  63. mmr_unlock(CTRL_MMR0_BASE, 3);
  64. mmr_unlock(CTRL_MMR0_BASE, 6);
  65. mmr_unlock(CTRL_MMR0_BASE, 7);
  66. }
  67. /*
  68. * This uninitialized global variable would normal end up in the .bss section,
  69. * but the .bss is cleared between writing and reading this variable, so move
  70. * it to the .data section.
  71. */
  72. u32 bootindex __attribute__((section(".data")));
  73. static void store_boot_index_from_rom(void)
  74. {
  75. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  76. }
  77. #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
  78. void k3_mmc_stop_clock(void)
  79. {
  80. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  81. struct mmc *mmc = find_mmc_device(0);
  82. if (!mmc)
  83. return;
  84. mmc->saved_clock = mmc->clock;
  85. mmc_set_clock(mmc, 0, true);
  86. }
  87. }
  88. void k3_mmc_restart_clock(void)
  89. {
  90. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  91. struct mmc *mmc = find_mmc_device(0);
  92. if (!mmc)
  93. return;
  94. mmc_set_clock(mmc, mmc->saved_clock, false);
  95. }
  96. }
  97. #else
  98. void k3_mmc_stop_clock(void) {}
  99. void k3_mmc_restart_clock(void) {}
  100. #endif
  101. #if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
  102. #define CTRLMMR_SERDES0_CTRL 0x00104080
  103. #define PCIE_LANE0 0x1
  104. static int fixup_usb_boot(void)
  105. {
  106. int ret;
  107. switch (spl_boot_device()) {
  108. case BOOT_DEVICE_USB:
  109. /*
  110. * If bootmode is Host bootmode, fixup the dr_mode to host
  111. * before the dwc3 bind takes place
  112. */
  113. ret = fdt_find_and_setprop((void *)gd->fdt_blob,
  114. "/interconnect@100000/dwc3@4000000/usb@10000",
  115. "dr_mode", "host", 11, 0);
  116. if (ret)
  117. printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
  118. ret);
  119. fallthrough;
  120. case BOOT_DEVICE_DFU:
  121. /*
  122. * The serdes mux between PCIe and USB3 needs to be set to PCIe for
  123. * accessing the interface at USB 2.0
  124. */
  125. writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
  126. default:
  127. break;
  128. }
  129. return 0;
  130. }
  131. int fdtdec_board_setup(const void *fdt_blob)
  132. {
  133. return fixup_usb_boot();
  134. }
  135. #endif
  136. void board_init_f(ulong dummy)
  137. {
  138. #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  139. struct udevice *dev;
  140. size_t pool_size;
  141. void *pool_addr;
  142. int ret;
  143. #endif
  144. /*
  145. * Cannot delay this further as there is a chance that
  146. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  147. */
  148. store_boot_index_from_rom();
  149. /* Make all control module registers accessible */
  150. ctrl_mmr_unlock();
  151. #ifdef CONFIG_CPU_V7R
  152. disable_linefill_optimization();
  153. setup_k3_mpu_regions();
  154. #endif
  155. /* Init DM early in-order to invoke system controller */
  156. spl_early_init();
  157. #ifdef CONFIG_K3_EARLY_CONS
  158. /*
  159. * Allow establishing an early console as required for example when
  160. * doing a UART-based boot. Note that this console may not "survive"
  161. * through a SYSFW PM-init step and will need a re-init in some way
  162. * due to changing module clock frequencies.
  163. */
  164. early_console_init();
  165. #endif
  166. #ifdef CONFIG_K3_LOAD_SYSFW
  167. /*
  168. * Initialize an early full malloc environment. Do so by allocating a
  169. * new malloc area inside the currently active pre-relocation "first"
  170. * malloc pool of which we use all that's left.
  171. */
  172. pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
  173. pool_addr = malloc(pool_size);
  174. if (!pool_addr)
  175. panic("ERROR: Can't allocate full malloc pool!\n");
  176. mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
  177. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  178. debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
  179. __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
  180. /*
  181. * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  182. * regardless of the result of pinctrl. Do this without probing the
  183. * device, but instead by searching the device that would request the
  184. * given sequence number if probed. The UART will be used by the system
  185. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  186. * to initialize its pin settings.
  187. */
  188. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
  189. if (!ret)
  190. pinctrl_select_state(dev, "default");
  191. /*
  192. * Load, start up, and configure system controller firmware while
  193. * also populating the SYSFW post-PM configuration callback hook.
  194. */
  195. k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
  196. /* Prepare console output */
  197. preloader_console_init();
  198. /* Disable ROM configured firewalls right after loading sysfw */
  199. #ifdef CONFIG_TI_SECURE_DEVICE
  200. remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
  201. remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
  202. #endif
  203. #else
  204. /* Prepare console output */
  205. preloader_console_init();
  206. #endif
  207. /* Output System Firmware version info */
  208. k3_sysfw_print_ver();
  209. /* Perform EEPROM-based board detection */
  210. do_board_detect();
  211. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  212. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
  213. &dev);
  214. if (ret)
  215. printf("AVS init failed: %d\n", ret);
  216. #endif
  217. #ifdef CONFIG_K3_AM654_DDRSS
  218. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  219. if (ret)
  220. panic("DRAM init failed: %d\n", ret);
  221. #endif
  222. spl_enable_dcache();
  223. }
  224. u32 spl_mmc_boot_mode(const u32 boot_device)
  225. {
  226. #if defined(CONFIG_SUPPORT_EMMC_BOOT)
  227. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  228. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  229. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  230. /* eMMC boot0 mode is only supported for primary boot */
  231. if (bootindex == K3_PRIMARY_BOOTMODE &&
  232. bootmode == BOOT_DEVICE_MMC1)
  233. return MMCSD_MODE_EMMCBOOT;
  234. #endif
  235. /* Everything else use filesystem if available */
  236. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  237. return MMCSD_MODE_FS;
  238. #else
  239. return MMCSD_MODE_RAW;
  240. #endif
  241. }
  242. static u32 __get_backup_bootmedia(u32 devstat)
  243. {
  244. u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  245. CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  246. switch (bkup_boot) {
  247. case BACKUP_BOOT_DEVICE_USB:
  248. return BOOT_DEVICE_USB;
  249. case BACKUP_BOOT_DEVICE_UART:
  250. return BOOT_DEVICE_UART;
  251. case BACKUP_BOOT_DEVICE_ETHERNET:
  252. return BOOT_DEVICE_ETHERNET;
  253. case BACKUP_BOOT_DEVICE_MMC2:
  254. {
  255. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  256. CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  257. if (port == 0x0)
  258. return BOOT_DEVICE_MMC1;
  259. return BOOT_DEVICE_MMC2;
  260. }
  261. case BACKUP_BOOT_DEVICE_SPI:
  262. return BOOT_DEVICE_SPI;
  263. case BACKUP_BOOT_DEVICE_HYPERFLASH:
  264. return BOOT_DEVICE_HYPERFLASH;
  265. case BACKUP_BOOT_DEVICE_I2C:
  266. return BOOT_DEVICE_I2C;
  267. };
  268. return BOOT_DEVICE_RAM;
  269. }
  270. static u32 __get_primary_bootmedia(u32 devstat)
  271. {
  272. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  273. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  274. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  275. bootmode = BOOT_DEVICE_SPI;
  276. if (bootmode == BOOT_DEVICE_MMC2) {
  277. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
  278. CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
  279. if (port == 0x0)
  280. bootmode = BOOT_DEVICE_MMC1;
  281. } else if (bootmode == BOOT_DEVICE_MMC1) {
  282. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
  283. CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
  284. if (port == 0x1)
  285. bootmode = BOOT_DEVICE_MMC2;
  286. } else if (bootmode == BOOT_DEVICE_DFU) {
  287. u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
  288. CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
  289. if (mode == 0x2)
  290. bootmode = BOOT_DEVICE_USB;
  291. }
  292. return bootmode;
  293. }
  294. u32 spl_boot_device(void)
  295. {
  296. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  297. if (bootindex == K3_PRIMARY_BOOTMODE)
  298. return __get_primary_bootmedia(devstat);
  299. else
  300. return __get_backup_bootmedia(devstat);
  301. }
  302. #endif
  303. #ifdef CONFIG_SYS_K3_SPL_ATF
  304. #define AM6_DEV_MCU_RTI0 134
  305. #define AM6_DEV_MCU_RTI1 135
  306. #define AM6_DEV_MCU_ARMSS0_CPU0 159
  307. #define AM6_DEV_MCU_ARMSS0_CPU1 245
  308. void release_resources_for_core_shutdown(void)
  309. {
  310. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  311. struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
  312. struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
  313. int ret;
  314. u32 i;
  315. const u32 put_device_ids[] = {
  316. AM6_DEV_MCU_RTI0,
  317. AM6_DEV_MCU_RTI1,
  318. };
  319. /* Iterate through list of devices to put (shutdown) */
  320. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  321. u32 id = put_device_ids[i];
  322. ret = dev_ops->put_device(ti_sci, id);
  323. if (ret)
  324. panic("Failed to put device %u (%d)\n", id, ret);
  325. }
  326. const u32 put_core_ids[] = {
  327. AM6_DEV_MCU_ARMSS0_CPU1,
  328. AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  329. };
  330. /* Iterate through list of cores to put (shutdown) */
  331. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  332. u32 id = put_core_ids[i];
  333. /*
  334. * Queue up the core shutdown request. Note that this call
  335. * needs to be followed up by an actual invocation of an WFE
  336. * or WFI CPU instruction.
  337. */
  338. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  339. if (ret)
  340. panic("Failed sending core %u shutdown message (%d)\n",
  341. id, ret);
  342. }
  343. }
  344. #endif