fsl,mpc83xx-mem-controller.txt 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314
  1. MPC83xx RAM controller
  2. This driver supplies support for the embedded RAM controller on MCP83xx-series
  3. SoCs.
  4. For static configuration mode, each controller node should have child nodes
  5. describing the actual RAM modules installed.
  6. Controller node
  7. ===============
  8. Required properties:
  9. - compatible: Must be "fsl,mpc83xx-mem-controller"
  10. - reg: The address of the RAM controller's register space
  11. - #address-cells: Must be 2
  12. - #size-cells: Must be 1
  13. - driver_software_override: DDR driver software override is enabled (1) or
  14. disabled (0)
  15. - p_impedance_override: DDR driver software p-impedance override; possible
  16. values:
  17. * DSO_P_IMPEDANCE_HIGHEST_Z
  18. * DSO_P_IMPEDANCE_MUCH_HIGHER_Z
  19. * DSO_P_IMPEDANCE_HIGHER_Z
  20. * DSO_P_IMPEDANCE_NOMINAL
  21. * DSO_P_IMPEDANCE_LOWER_Z
  22. - n_impedance_override: DDR driver software n-impedance override; possible
  23. values:
  24. * DSO_N_IMPEDANCE_HIGHEST_Z
  25. * DSO_N_IMPEDANCE_MUCH_HIGHER_Z
  26. * DSO_N_IMPEDANCE_HIGHER_Z
  27. * DSO_N_IMPEDANCE_NOMINAL
  28. * DSO_N_IMPEDANCE_LOWER_Z
  29. - odt_termination_value: ODT termination value for I/Os; possible values:
  30. * ODT_TERMINATION_75_OHM
  31. * ODT_TERMINATION_150_OHM
  32. - ddr_type: Selects voltage level for DDR pads; possible
  33. values:
  34. * DDR_TYPE_DDR2_1_8_VOLT
  35. * DDR_TYPE_DDR1_2_5_VOLT
  36. - mvref_sel: Determine where MVREF_SEL signal is generated;
  37. possible values:
  38. * MVREF_SEL_EXTERNAL
  39. * MVREF_SEL_INTERNAL_GVDD
  40. - m_odr: Disable memory transaction reordering; possible
  41. values:
  42. * M_ODR_ENABLE
  43. * M_ODR_DISABLE
  44. - clock_adjust: Clock adjust; possible values:
  45. * CLOCK_ADJUST_025
  46. * CLOCK_ADJUST_05
  47. * CLOCK_ADJUST_075
  48. * CLOCK_ADJUST_1
  49. - ext_refresh_rec: Extended refresh recovery time; possible values:
  50. 0, 16, 32, 48, 64, 80, 96, 112
  51. - read_to_write: Read-to-write turnaround; possible values:
  52. 0, 1, 2, 3
  53. - write_to_read: Write-to-read turnaround; possible values:
  54. 0, 1, 2, 3
  55. - read_to_read: Read-to-read turnaround; possible values:
  56. 0, 1, 2, 3
  57. - write_to_write: Write-to-write turnaround; possible values:
  58. 0, 1, 2, 3
  59. - active_powerdown_exit: Active powerdown exit timing; possible values:
  60. 1, 2, 3, 4, 5, 6, 7
  61. - precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
  62. 1, 2, 3, 4, 5, 6, 7
  63. - odt_powerdown_exit: ODT powerdown exit timing; possible values:
  64. 0, 1, 2, 3, 4, 5, 6, 7, 8,
  65. 9, 10, 11, 12, 13, 14, 15
  66. - mode_reg_set_cycle: Mode register set cycle time; possible values:
  67. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
  68. - precharge_to_activate: Precharge-to-acitvate interval; possible values:
  69. 1, 2, 3, 4, 5, 6, 7
  70. - activate_to_precharge: Activate to precharge interval; possible values:
  71. 4, 5, 6, 7, 8, 9, 10, 11, 12,
  72. 13, 14, 15, 16, 17, 18, 19
  73. - activate_to_readwrite: Activate to read/write interval for SDRAM;
  74. possible values:
  75. 1, 2, 3, 4, 5, 6, 7
  76. - mcas_latency: MCAS latency from READ command; possible values:
  77. * CASLAT_20
  78. * CASLAT_25
  79. * CASLAT_30
  80. * CASLAT_35
  81. * CASLAT_40
  82. * CASLAT_45
  83. * CASLAT_50
  84. * CASLAT_55
  85. * CASLAT_60
  86. * CASLAT_65
  87. * CASLAT_70
  88. * CASLAT_75
  89. * CASLAT_80
  90. - refresh_recovery: Refresh recovery time; possible values:
  91. 8, 9, 10, 11, 12, 13, 14, 15,
  92. 16, 17, 18, 19, 20, 21, 22, 23
  93. - last_data_to_precharge: Last data to precharge minimum interval; possible
  94. values:
  95. 1, 2, 3, 4, 5, 6, 7
  96. - activate_to_activate: Activate-to-activate interval; possible values:
  97. 1, 2, 3, 4, 5, 6, 7
  98. - last_write_data_to_read: Last write data pair to read command issue
  99. interval; possible values:
  100. 1, 2, 3, 4, 5, 6, 7
  101. - additive_latency: Additive latency; possible values:
  102. 0, 1, 2, 3, 4, 5
  103. - mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
  104. * READ_LAT
  105. * READ_LAT_PLUS_1_4
  106. * READ_LAT_PLUS_1_2
  107. * READ_LAT_PLUS_3_4
  108. * READ_LAT_PLUS_1
  109. * READ_LAT_PLUS_5_4
  110. * READ_LAT_PLUS_3_2
  111. * READ_LAT_PLUS_7_4
  112. * READ_LAT_PLUS_2
  113. * READ_LAT_PLUS_9_4
  114. * READ_LAT_PLUS_5_2
  115. * READ_LAT_PLUS_11_4
  116. * READ_LAT_PLUS_3
  117. * READ_LAT_PLUS_13_4
  118. * READ_LAT_PLUS_7_2
  119. * READ_LAT_PLUS_15_4
  120. * READ_LAT_PLUS_4
  121. * READ_LAT_PLUS_17_4
  122. * READ_LAT_PLUS_9_2
  123. * READ_LAT_PLUS_19_4
  124. - write_latency: Write latency; possible values:
  125. 1, 2, 3, 4, 5, 6, 7
  126. - read_to_precharge: Read to precharge; possible values:
  127. 1, 2, 3, 4
  128. - write_cmd_to_write_data: Write command to write data strobe timing
  129. adjustment; possible values:
  130. * CLOCK_DELAY_0
  131. * CLOCK_DELAY_1_4
  132. * CLOCK_DELAY_1_2
  133. * CLOCK_DELAY_3_4
  134. * CLOCK_DELAY_1
  135. * CLOCK_DELAY_5_4
  136. * CLOCK_DELAY_3_2
  137. - minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
  138. 1, 2, 3, 4
  139. - four_activates_window: Window for four activates; possible values:
  140. 1, 2, 3, 4 8, 9, 10, 11, 12,
  141. 13, 14, 15, 16, 17, 18, 19
  142. - self_refresh: Self refresh (during sleep); possible values:
  143. * SREN_DISABLE
  144. * SREN_ENABLE
  145. - ecc: Support for ECC; possible values:
  146. * ECC_DISABLE
  147. * ECC_ENABLE
  148. - registered_dram: Support for registered DRAM; possible values:
  149. * RD_DISABLE
  150. * RD_ENABLE
  151. - sdram_type: Type of SDRAM device to be used; possible values:
  152. * TYPE_DDR1
  153. * TYPE_DDR2
  154. - dynamic_power_management: Dynamic power management mode; possible values:
  155. * DYN_PWR_DISABLE
  156. * DYN_PWR_ENABLE
  157. - databus_width: DRAM data bus width; possible values
  158. * DATA_BUS_WIDTH_16
  159. * DATA_BUS_WIDTH_32
  160. - nc_auto_precharge: Non-concurrent auto-precharge; possible values:
  161. * NCAP_DISABLE
  162. * NCAP_ENABLE
  163. - timing_2t: 2T timing; possible values:
  164. * TIMING_1T
  165. * TIMING_2T
  166. - bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
  167. values:
  168. * INTERLEAVE_NONE
  169. * INTERLEAVE_1_AND_2
  170. - precharge_bit_8: Precharge bin 8; possible values
  171. * PRECHARGE_MA_10
  172. * PRECHARGE_MA_8
  173. - half_strength: Global half-strength override; possible values:
  174. * STRENGTH_FULL
  175. * STRENGTH_HALF
  176. - bypass_initialization: Bypass initialization; possible values:
  177. * INITIALIZATION_DONT_BYPASS
  178. * INITIALIZATION_BYPASS
  179. - force_self_refresh: Force self refresh; possible values:
  180. * MODE_NORMAL
  181. * MODE_REFRESH
  182. - dll_reset: DLL reset; possible values:
  183. * DLL_RESET_ENABLE
  184. * DLL_RESET_DISABLE
  185. - dqs_config: DQS configuration; possible values:
  186. * DQS_TRUE
  187. - odt_config: ODT configuration; possible values:
  188. * ODT_ASSERT_NEVER
  189. * ODT_ASSERT_WRITES
  190. * ODT_ASSERT_READS
  191. * ODT_ASSERT_ALWAYS
  192. - posted_refreshes: Number of posted refreshes
  193. 1, 2, 3, 4, 5, 6, 7, 8
  194. - sdmode: Initial value loaded into the DDR SDRAM mode
  195. register
  196. - esdmode: Initial value loaded into the DDR SDRAM extended
  197. mode register
  198. - esdmode2: Initial value loaded into the DDR SDRAM extended
  199. mode 2 register
  200. - esdmode3: Initial value loaded into the DDR SDRAM extended
  201. mode 3 register
  202. - refresh_interval: Refresh interval; possible values:
  203. 0 - 65535
  204. - precharge_interval: Precharge interval; possible values:
  205. 0 - 16383
  206. RAM module node:
  207. ================
  208. Required properties:
  209. - reg: A triple <cs addr size>, which consists of:
  210. * cs - the chipselect used to drive this RAM module
  211. * addr - the address where this RAM module's memory is map
  212. to in the global memory space
  213. * size - the size of the RAM module's memory in bytes
  214. - auto_precharge: Chip select auto-precharge; possible values:
  215. * AUTO_PRECHARGE_ENABLE
  216. * AUTO_PRECHARGE_DISABLE
  217. - odt_rd_cfg: ODT for reads configuration; possible values:
  218. * ODT_RD_NEVER
  219. * ODT_RD_ONLY_CURRENT
  220. * ODT_RD_ONLY_OTHER_CS
  221. * ODT_RD_ONLY_OTHER_DIMM
  222. * ODT_RD_ALL
  223. - odt_wr_cfg: ODT for writes configuration; possible values:
  224. * ODT_WR_NEVER
  225. * ODT_WR_ONLY_CURRENT
  226. * ODT_WR_ONLY_OTHER_CS
  227. * ODT_WR_ONLY_OTHER_DIMM
  228. * ODT_WR_ALL
  229. - bank_bits: Number of bank bits for SDRAM on chip select; possible
  230. values:
  231. 2, 3
  232. - row_bits: Number of row bits for SDRAM on chip select; possible values:
  233. 12, 13, 14
  234. - col_bits: Number of column bits for SDRAM on chip select; possible
  235. values:
  236. 8, 9, 10, 11
  237. Example:
  238. memory@2000 {
  239. #address-cells = <2>;
  240. #size-cells = <1>;
  241. compatible = "fsl,mpc83xx-mem-controller";
  242. reg = <0x2000 0x1000>;
  243. device_type = "memory";
  244. u-boot,dm-pre-reloc;
  245. driver_software_override = <DSO_ENABLE>;
  246. p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
  247. n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
  248. odt_termination_value = <ODT_TERMINATION_150_OHM>;
  249. ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
  250. clock_adjust = <CLOCK_ADJUST_05>;
  251. read_to_write = <0>;
  252. write_to_read = <0>;
  253. read_to_read = <0>;
  254. write_to_write = <0>;
  255. active_powerdown_exit = <2>;
  256. precharge_powerdown_exit = <6>;
  257. odt_powerdown_exit = <8>;
  258. mode_reg_set_cycle = <2>;
  259. precharge_to_activate = <2>;
  260. activate_to_precharge = <6>;
  261. activate_to_readwrite = <2>;
  262. mcas_latency = <CASLAT_40>;
  263. refresh_recovery = <17>;
  264. last_data_to_precharge = <2>;
  265. activate_to_activate = <2>;
  266. last_write_data_to_read = <2>;
  267. additive_latency = <0>;
  268. mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
  269. write_latency = <3>;
  270. read_to_precharge = <2>;
  271. write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
  272. minimum_cke_pulse_width = <3>;
  273. four_activates_window = <5>;
  274. self_refresh = <SREN_ENABLE>;
  275. sdram_type = <TYPE_DDR2>;
  276. databus_width = <DATA_BUS_WIDTH_32>;
  277. force_self_refresh = <MODE_NORMAL>;
  278. dll_reset = <DLL_RESET_ENABLE>;
  279. dqs_config = <DQS_TRUE>;
  280. odt_config = <ODT_ASSERT_READS>;
  281. posted_refreshes = <1>;
  282. refresh_interval = <2084>;
  283. precharge_interval = <256>;
  284. sdmode = <0x0242>;
  285. esdmode = <0x0440>;
  286. ram@0 {
  287. reg = <0x0 0x0 0x8000000>;
  288. compatible = "nanya,nt5tu64m16hg";
  289. odt_rd_cfg = <ODT_RD_NEVER>;
  290. odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
  291. bank_bits = <3>;
  292. row_bits = <13>;
  293. col_bits = <10>;
  294. };
  295. };